xuartps_hw.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

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/**
*
* @file xuartps_hw.h
*
* This header file contains the hardware interface of an XUartPs device.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who    Date	Changes
* ----- ------ -------- ----------------------------------------------
* 1.00	drg/jz 01/12/10 First Release
* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
* </pre>
*
******************************************************************************/

#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
#define XUARTPS_HW_H		/* by using protection macros */

#ifdef __cplusplus
extern "C" {
#endif

/***************************** Include Files *********************************/

#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"

/************************** Constant Definitions *****************************/

/** @name Register Map
 *
 * Register offsets for the UART.
 * @{
 */
#define XUARTPS_CR_OFFSET	0x00  /**< Control Register [8:0] */
#define XUARTPS_MR_OFFSET	0x04  /**< Mode Register [10:0] */
#define XUARTPS_IER_OFFSET	0x08  /**< Interrupt Enable [10:0] */
#define XUARTPS_IDR_OFFSET	0x0C  /**< Interrupt Disable [10:0] */
#define XUARTPS_IMR_OFFSET	0x10  /**< Interrupt Mask [10:0] */
#define XUARTPS_ISR_OFFSET	0x14  /**< Interrupt Status [10:0]*/
#define XUARTPS_BAUDGEN_OFFSET	0x18  /**< Baud Rate Generator [15:0] */
#define XUARTPS_RXTOUT_OFFSET	0x1C  /**< RX Timeout [7:0] */
#define XUARTPS_RXWM_OFFSET	0x20  /**< RX FIFO Trigger Level [5:0] */
#define XUARTPS_MODEMCR_OFFSET	0x24  /**< Modem Control [5:0] */
#define XUARTPS_MODEMSR_OFFSET	0x28  /**< Modem Status [8:0] */
#define XUARTPS_SR_OFFSET	0x2C  /**< Channel Status [11:0] */
#define XUARTPS_FIFO_OFFSET	0x30  /**< FIFO [15:0] or [7:0] */
#define XUARTPS_BAUDDIV_OFFSET	0x34  /**< Baud Rate Divider [7:0] */
#define XUARTPS_FLOWDEL_OFFSET	0x38  /**< Flow Delay [15:0] */
#define XUARTPS_TXWM_OFFSET	0x44  /**< TX FIFO Trigger Level [5:0] */
/* @} */

/** @name Control Register
 *
 * The Control register (CR) controls the major functions of the device.
 *
 * Control Register Bit Definition
 */

#define XUARTPS_CR_STOPBRK	0x00000100  /**< Stop transmission of break */
#define XUARTPS_CR_STARTBRK	0x00000080  /**< Set break */
#define XUARTPS_CR_TORST	0x00000040  /**< RX timeout counter restart */
#define XUARTPS_CR_TX_DIS	0x00000020  /**< TX disabled. */
#define XUARTPS_CR_TX_EN	0x00000010  /**< TX enabled */
#define XUARTPS_CR_RX_DIS	0x00000008  /**< RX disabled. */
#define XUARTPS_CR_RX_EN	0x00000004  /**< RX enabled */
#define XUARTPS_CR_EN_DIS_MASK	0x0000003C  /**< Enable/disable Mask */
#define XUARTPS_CR_TXRST	0x00000002  /**< TX logic reset */
#define XUARTPS_CR_RXRST	0x00000001  /**< RX logic reset */
/* @}*/


/** @name Mode Register
 *
 * The mode register (MR) defines the mode of transfer as well as the data
 * format. If this register is modified during transmission or reception,
 * data validity cannot be guaranteed.
 *
 * Mode Register Bit Definition
 * @{
 */

#define XUARTPS_MR_CCLK			0x00000400 /**< Input clock selection */
#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300 /**< Remote loopback mode */
#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200 /**< Local loopback mode */
#define XUARTPS_MR_CHMODE_ECHO		0x00000100 /**< Auto echo mode */
#define XUARTPS_MR_CHMODE_NORM		0x00000000 /**< Normal mode */
#define XUARTPS_MR_CHMODE_SHIFT			8  /**< Mode shift */
#define XUARTPS_MR_CHMODE_MASK		0x00000300 /**< Mode mask */
#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080 /**< 2 stop bits */
#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040 /**< 1.5 stop bits */
#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000 /**< 1 stop bit */
#define XUARTPS_MR_STOPMODE_SHIFT		6  /**< Stop bits shift */
#define XUARTPS_MR_STOPMODE_MASK	0x000000A0 /**< Stop bits mask */
#define XUARTPS_MR_PARITY_NONE		0x00000020 /**< No parity mode */
#define XUARTPS_MR_PARITY_MARK		0x00000018 /**< Mark parity mode */
#define XUARTPS_MR_PARITY_SPACE		0x00000010 /**< Space parity mode */
#define XUARTPS_MR_PARITY_ODD		0x00000008 /**< Odd parity mode */
#define XUARTPS_MR_PARITY_EVEN		0x00000000 /**< Even parity mode */
#define XUARTPS_MR_PARITY_SHIFT		3  /**< Parity setting shift */
#define XUARTPS_MR_PARITY_MASK		0x00000038 /**< Parity mask */
#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006 /**< 6 bits data */
#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004 /**< 7 bits data */
#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000 /**< 8 bits data */
#define XUARTPS_MR_CHARLEN_SHIFT		1  /**< Data Length shift */
#define XUARTPS_MR_CHARLEN_MASK		0x00000006 /**< Data length mask */
#define XUARTPS_MR_CLKSEL		0x00000001 /**< Input clock selection */
/* @} */


/** @name Interrupt Registers
 *
 * Interrupt control logic uses the interrupt enable register (IER) and the
 * interrupt disable register (IDR) to set the value of the bits in the
 * interrupt mask register (IMR). The IMR determines whether to pass an
 * interrupt to the interrupt status register (ISR).
 * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
 * Reading either IER or IDR returns 0x00.
 *
 * All four registers have the same bit definitions.
 *
 * @{
 */

#define XUARTPS_IXR_DMS		0x00000200 /**< Modem status change interrupt */
#define XUARTPS_IXR_TOUT	0x00000100 /**< Timeout error interrupt */
#define XUARTPS_IXR_PARITY 	0x00000080 /**< Parity error interrupt */
#define XUARTPS_IXR_FRAMING	0x00000040 /**< Framing error interrupt */
#define XUARTPS_IXR_OVER	0x00000020 /**< Overrun error interrupt */
#define XUARTPS_IXR_TXFULL 	0x00000010 /**< TX FIFO full interrupt. */
#define XUARTPS_IXR_TXEMPTY	0x00000008 /**< TX FIFO empty interrupt. */
#define XUARTPS_IXR_RXFULL 	0x00000004 /**< RX FIFO full interrupt. */
#define XUARTPS_IXR_RXEMPTY	0x00000002 /**< RX FIFO empty interrupt. */
#define XUARTPS_IXR_RXOVR  	0x00000001 /**< RX FIFO trigger interrupt. */
#define XUARTPS_IXR_MASK	0x000003FF /**< Valid bit mask */
/* @} */


/** @name Baud Rate Generator Register
 *
 * The baud rate generator control register (BRGR) is a 16 bit register that
 * controls the receiver bit sample clock and baud rate.
 * Valid values are 1 - 65535.
 *
 * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
 * in the MR register.
 * @{
 */
#define XUARTPS_BAUDGEN_DISABLE		0x00000000 /**< Disable clock */
#define XUARTPS_BAUDGEN_MASK		0x0000FFFF /**< Valid bits mask */

/** @name Baud Divisor Rate register