xscugic_hw.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

 * Each bit pair describes the configuration for an INT_ID.
 * SFI    Read Only    b10 always
 * PPI    Read Only    depending on how the PPIs are configured.
 *                    b01    Active HIGH level sensitive
 *                    b11 Rising edge sensitive
 * SPI                LSB is read only.
 *                    b01    Active HIGH level sensitive
 *                    b11 Rising edge sensitive/
 * There are registers for each of the CPU interfaces at offset 0xC00 through
 * 0xC04. With up to 8 registers aliased to each address.
 * A register set for the SPI interrupts is available to all CPU interfaces.
 * There are up to 255 of these registers staring at location 0xC08.
 * @{
 */
#define XSCUGIC_INT_CFG_MASK    0x00000003    /**< */
/* @} */

/** @name  PPI Status Register
 * Enables an external AMBA master to access the status of the PPI inputs.
 * A CPU can only read the status of its local PPI signals and cannot read the
 * status for other CPUs.
 * This register is aliased for each CPU interface.
 * @{
 */
#define XSCUGIC_PPI_C15_MASK	0x00008000    /**< PPI Status */
#define XSCUGIC_PPI_C14_MASK	0x00004000    /**< PPI Status */
#define XSCUGIC_PPI_C13_MASK	0x00002000    /**< PPI Status */
#define XSCUGIC_PPI_C12_MASK	0x00001000    /**< PPI Status */
#define XSCUGIC_PPI_C11_MASK	0x00000800    /**< PPI Status */
#define XSCUGIC_PPI_C10_MASK	0x00000400    /**< PPI Status */
#define XSCUGIC_PPI_C09_MASK	0x00000200    /**< PPI Status */
#define XSCUGIC_PPI_C08_MASK	0x00000100    /**< PPI Status */
#define XSCUGIC_PPI_C07_MASK	0x00000080    /**< PPI Status */
#define XSCUGIC_PPI_C06_MASK	0x00000040    /**< PPI Status */
#define XSCUGIC_PPI_C05_MASK	0x00000020    /**< PPI Status */
#define XSCUGIC_PPI_C04_MASK	0x00000010    /**< PPI Status */
#define XSCUGIC_PPI_C03_MASK	0x00000008    /**< PPI Status */
#define XSCUGIC_PPI_C02_MASK	0x00000004    /**< PPI Status */
#define XSCUGIC_PPI_C01_MASK	0x00000002    /**< PPI Status */
#define XSCUGIC_PPI_C00_MASK	0x00000001    /**< PPI Status */
/* @} */

/** @name  SPI Status Register 0xd04-0xd7C
 * Enables an external AMBA master to access the status of the SPI inputs.
 * There are up to 63 registers if the maximum number of SPI inputs are
 * configured.
 * @{
 */
#define XSCUGIC_SPI_N_MASK    0x00000001    /**< Each bit corresponds to an SPI
					     input */
/* @} */

/** @name  AHB Configuration Register
 * Provides the status of the CFGBIGEND input signal and allows the endianess
 * of the GIC to be set.
 * @{
 */
#define XSCUGIC_AHB_END_MASK       0x00000004    /**< 0-GIC uses little Endian,
                                                  1-GIC uses Big Endian */
#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002    /**< 0-Uses CFGBIGEND control,
                                                  1-use the AHB_END bit */
#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001    /**< State of CFGBIGEND */

/* @} */

/** @name  Software Triggered Interrupt Register
 * Controls issueing of software interrupts.
 * @{
 */
#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000
#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000    /**< Target List filter
                                                            b00-Use the target List
                                                            b01-All CPUs except requester
                                                            b10-To Requester
                                                            b11-reserved */
#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000    /**< CPU Target list */
#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000    /**< 0= Use a secure interrupt */
#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000F    /**< Set to the INTID
                                                        signaled to the CPU*/
/* @} */

/** @name CPU Interface Register Map
 *
 * Define the offsets from the base address for all CPU registers of the
 * interrupt controller, some registers may be reserved in the hardware device.
 * @{
 */
#define XSCUGIC_CONTROL_OFFSET		0x00000000 /**< CPU Interface Control
						 	Register */
#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004 /**< Priority Mask Reg */
#define XSCUGIC_BIN_PT_OFFSET		0x00000008 /**< Binary Point Register */
#define XSCUGIC_INT_ACK_OFFSET		0x0000000C /**< Interrupt ACK Reg */
#define XSCUGIC_EOI_OFFSET		0x00000010 /**< End of Interrupt Reg */
#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014 /**< Running Priority Reg */
#define XSCUGIC_HI_PEND_OFFSET		0x00000018 /**< Highest Pending Interrupt
							Register */
#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001C /**< Aliased non-Secure
						        Binary Point Register */

/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
 * to. */
/* @} */


/** @name Control Register
 * CPU Interface Control register definitions
 * All bits are defined here although some are not available in the non-secure
 * mode.
 * @{
 */
#define XSCUGIC_CNTR_SBPR_MASK	0x00000010    /**< Secure Binary Pointer,
                                                 0=separate registers,
                                                 1=both use bin_pt_s */
#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008    /**< Use nFIQ_C for secure
                                                  interrupts,
                                                  0= use IRQ for both,
                                                  1=Use FIQ for secure, IRQ for non*/
#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004    /**< Ack control for secure or non secure */
#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002    /**< Non Secure enable */
#define XSCUGIC_CNTR_EN_S_MASK		0x00000001    /**< Secure enable, 0=Disabled, 1=Enabled */
/* @} */

/** @name Priority Mask Register
 * Priority Mask register definitions
 * The CPU interface does not send interrupt if the level of the interrupt is
 * lower than the level of the register.
 * @{
 */
#define XSCUGIC_PRIORITY_MASK		0x000000FF    /**< All interrupts */
/* @} */

/** @name Binary Point Register
 * Binary Point register definitions
 * @{
 */

#define XSCUGIC_BIN_PT_MASK	0x00000007  /**< Binary point mask value
						Value  Secure  Non-secure
						b000    0xFE    0xFF
						b001    0xFC    0xFE
						b010    0xF8    0xFC
						b011    0xF0    0xF8
						b100    0xE0    0xF0
						b101    0xC0    0xE0
						b110    0x80    0xC0
						b111    0x00    0x80
						*/
/*@}*/

/** @name Interrupt Acknowledge Register
 * Interrupt Acknowledge register definitions
 * Identifies the current Pending interrupt, and the CPU ID for software
 * interrupts.
 */
#define XSCUGIC_ACK_INTID_MASK		0x000003FF /**< Interrupt ID */
#define XSCUGIC_CPUID_MASK		0x00000C00 /**< CPU ID */
/* @} */

/** @name End of Interrupt Register
 * End of Interrupt register definitions
 * Allows the CPU to signal the GIC when it completes an interrupt service
 * routine.
 */
#define XSCUGIC_EOI_INTID_MASK		0x000003FF /**< Interrupt ID */

/* @} */

/** @name Running Priority Register
 * Running Priority register definitions
 * Identifies the interrupt priority level of the highest priority active
 * interrupt.
 */
#define XSCUGIC_RUN_PRIORITY_MASK	0x00000FF    /**< Interrupt Priority */
/* @} */

/*
 * Highest Pending Interrupt register definitions
 * Identifies the interrupt priority of the highest priority pending interupt
 */
#define XSCUGIC_PEND_INTID_MASK		0x000003FF /**< Pending Interrupt ID */
#define XSCUGIC_CPUID_MASK		0x00000C00 /**< CPU ID */
/* @} */

/***************** Macros (Inline Functions) Definitions *********************/

/****************************************************************************/
/**
*
* Read the given Intc register.
*
* @param	BaseAddress is the base address of the device.
* @param	RegOffset is the register offset to be read
*
* @return	The 32-bit value of the register
*
* @note
* C-style signature:
*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReadReg(BaseAddress, RegOffset) \
	(Xil_In32((BaseAddress) + (RegOffset)))


/****************************************************************************/
/**
*
* Write the given Intc register.
*
* @param	BaseAddress is the base address of the device.
* @param	RegOffset is the register offset to be written
* @param	Data is the 32-bit value to write to the register
*
* @return	None.
*
* @note
* C-style signature:
*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)Data)))


/****************************************************************************/
/**
*
* Enable specific interrupt(s) in the interrupt controller.
*
* @param	DistBaseAddress is the Distributor Register base address of the
*		device
* @param	Int_Id is the ID of the interrupt source and should be in the
*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
*
* @return	None.
*
* @note		C-style signature:
*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id);
*
*****************************************************************************/
#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
	XScuGic_WriteReg((DistBaseAddress), \
			 XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32) * 4), \
			 (1 << (Int_Id % 32)))

/****************************************************************************/
/**
*
* Disable specific interrupt(s) in the interrupt controller.
*
* @param	DistBaseAddress is the Distributor Register base address of the
*		device
* @param	Int_Id is the ID of the interrupt source and should be in the
*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
*
*
* @return	None.
*
* @note		C-style signature:
*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id);
*
*****************************************************************************/
#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
	XScuGic_WriteReg((DistBaseAddress), \
			 XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32) * 4), \
			 (1 << (Int_Id % 32)))


/************************** Function Prototypes ******************************/

void XScuGic_DeviceInterruptHandler(void *DeviceId);
int  XScuGic_DeviceInitialize(u32 DeviceId);
void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId,
			     Xil_InterruptHandler Handler, void *CallBackRef);

/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif

#endif            /* end of protection macro */