xpm_counter.h

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/* $Id: xpm_counter.h,v 1.1.4.2 2011/10/27 07:32:23 sadanan Exp $ */
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/**
*
* @file xpm_counter.h
*
* This header file contains APIs for configuring and controlling the Cortex-A9
* Performance Monitor Events.
* Cortex-A9 Performance Monitor has 6 event counters which can be used to
* count a variety of events described in Coretx-A9 TRM. This file defines
* configurations, where value configures the event counters to count a
* set of events.
*
* Xpm_SetEvents can be used to set the event counters to count a set of events
* and Xpm_GetEventCounters can be used to read the counter values.
*
* @note
*
* This file doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
* being used for time keeping.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who  Date     Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sdm  07/11/11 First release
* </pre>
*
******************************************************************************/

#ifndef XPMCOUNTER_H /* prevent circular inclusions */
#define XPMCOUNTER_H /* by using protection macros */

/***************************** Include Files ********************************/

#include <stdint.h>
#include "xpseudo_asm.h"
#include "xil_types.h"

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

/************************** Constant Definitions ****************************/

/* Number of performance counters */
#define XPM_CTRCOUNT 6

/* The following constants define the Cortex-A9 Performance Monitor Events */

/*
 * Software increment. The register is incremented only on writes to the
 * Software Increment Register
 */
#define XPM_EVENT_SOFTINCR 0x00

/*
 * Instruction fetch that causes a refill at (at least) the lowest level(s) of
 * instruction or unified cache. Includes the speculative linefills in the
 * count
 */
#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01

/*
 * Instruction fetch that causes a TLB refill at (at least) the lowest level of
 * TLB. Includes the speculative requests in the count
 */
#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02

/*
 * Data read or write operation that causes a refill at (at least) the lowest
 * level(s)of data or unified cache. Counts the number of allocations performed
 * in the Data Cache due to a read or a write
 */
#define XPM_EVENT_DATA_CACHEREFILL 0x03

/*
 * Data read or write operation that causes a cache access at (at least) the
 * lowest level(s) of data or unified cache. This includes speculative reads
 */
#define XPM_EVENT_DATA_CACHEACCESS 0x04

/*
 * Data read or write operation that causes a TLB refill at (at least) the
 * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
 * CP15 Cache operation by MVA and CP15 VA to PA operations
 */
#define XPM_EVENT_DATA_TLBREFILL 0x05

/*
 * Data read architecturally executed. Counts the number of data read
 * instructions accepted by the Load Store Unit. This includes counting the
 * speculative and aborted LDR/LDM, as well as the reads due to the SWP
 * instructions
 */
#define XPM_EVENT_DATA_READS 0x06

/*
 * Data write architecturally executed. Counts the number of data write
 * instructions accepted by the Load Store Unit. This includes counting the
 * speculative and aborted STR/STM, as well as the writes due to the SWP
 * instructions
 */
#define XPM_EVENT_DATA_WRITE 0x07

/* Exception taken. Counts the number of exceptions architecturally taken.*/
#define XPM_EVENT_EXCEPTION 0x09

/* Exception return architecturally executed.*/
#define XPM_EVENT_EXCEPRETURN 0x0A

/*
 * Change to ContextID retired. Counts the number of instructions
 * architecturally executed writing into the ContextID Register
 */
#define XPM_EVENT_CHANGECONTEXT 0x0B

/*
 * Software change of PC, except by an exception, architecturally executed.
 * Count the number of PC changes architecturally executed, excluding the PC
 * changes due to taken exceptions
 */
#define XPM_EVENT_SW_CHANGEPC 0x0C

/*
 * Immediate branch architecturally executed (taken or not taken). This includes
 * the branches which are flushed due to a previous load/store which aborts
 * late
 */
#define XPM_EVENT_IMMEDBRANCH 0x0D

/*
 * Unaligned access architecturally executed. Counts the number of aborted
 * unaligned accessed architecturally executed, and the number of not-aborted
 * unaligned accesses, including the speculative ones
 */
#define XPM_EVENT_UNALIGNEDACCESS 0x0F

/*
 * Branch mispredicted/not predicted. Counts the number of mispredicted or
 * not-predicted branches executed. This includes the branches which are flushed
 * due to a previous load/store which aborts late
 */
#define XPM_EVENT_BRANCHMISS 0x10

/*
 * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
 * event is not exported on the PMUEVENT bus
 */
#define XPM_EVENT_CLOCKCYCLES 0x11

/*
 * Branches or other change in program flow that could have been predicted by
 * the branch prediction resources of the processor. This includes the branches
 * which are flushed due to a previous load/store which aborts late
 */
#define XPM_EVENT_BRANCHPREDICT 0x12

/*
 * Java bytecode execute. Counts the number of Java bytecodes being decoded,
 * including speculative ones
 */
#define XPM_EVENT_JAVABYTECODE 0x40

/*
 * Software Java bytecode executed. Counts the number of software java bytecodes
 * being decoded, including speculative ones
 */
#define XPM_EVENT_SWJAVABYTECODE 0x41

/*
 * Jazelle backward branches executed. Counts the number of Jazelle taken
 * branches being executed. This includes the branches which are flushed due
 * to a previous load/store which aborts late
 */
#define XPM_EVENT_JAVABACKBRANCH 0x42

/*
 * Coherent linefill miss Counts the number of coherent linefill requests
 * performed by the Cortex-A9 processor which also miss in all the other
 * Cortex-A9 processors, meaning that the request is sent to the external
 * memory
 */
#define XPM_EVENT_COHERLINEMISS 0x50

/*
 * Coherent linefill hit. Counts the number of coherent linefill requests
 * performed by the Cortex-A9 processor which hit in another Cortex-A9
 * processor, meaning that the linefill data is fetched directly from the
 * relevant Cortex-A9 cache
 */
#define XPM_EVENT_COHERLINEHIT 0x51

/*
 * Instruction cache dependent stall cycles. Counts the number of cycles where
 * the processor is ready to accept new instructions, but does not receive any
 * due to the instruction side not being able to provide any and the
 * instruction cache is currently performing at least one linefill
 */
#define XPM_EVENT_INSTRSTALL 0x60

/*
 * Data cache dependent stall cycles. Counts the number of cycles where the core
 * has some instructions that it cannot issue to any pipeline, and the Load
 * Store unit has at least one pending linefill request, and no pending
 */
#define XPM_EVENT_DATASTALL 0x61

/*
 * Main TLB miss stall cycles. Counts the number of cycles where the processor
 * is stalled waiting for the completion of translation table walks from the
 * main TLB. The processor stalls can be due to the instruction side not being
 * able to provide the instructions, or to the data side not being able to
 * provide the necessary data, due to them waiting for the main TLB translation
 * table walk to complete
 */
#define XPM_EVENT_MAINTLBSTALL 0x62

/*
 * Counts the number of STREX instructions architecturally executed and
 * passed
 */
#define XPM_EVENT_STREXPASS 0x63

/*
 * Counts the number of STREX instructions architecturally executed and
 * failed
 */
#define XPM_EVENT_STREXFAIL 0x64

/*
 * Data eviction. Counts the number of eviction requests due to a linefill in
 * the data cache
 */
#define XPM_EVENT_DATAEVICT 0x65

/*
 * Counts the number of cycles where the issue stage does not dispatch any
 * instruction because it is empty or cannot dispatch any instructions
 */
#define XPM_EVENT_NODISPATCH 0x66

/*
 * Counts the number of cycles where the issue stage is empty
 */
#define XPM_EVENT_ISSUEEMPTY 0x67

/*
 * Counts the number of instructions going through the Register Renaming stage.
 * This number is an approximate number of the total number of instructions