xemacps_hw.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

                                                         stat counters */
#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040 /**< Increment statistic
                                                         registers */
#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020 /**< Clear statistic
                                                         registers */
#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010 /**< Enable MDIO port */
#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008 /**< Enable transmit */
#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004 /**< Enable receive */
#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002 /**< local loopback */
/*@}*/

/** @name network configuration register bit definitions
 * @{
 */
#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000 /**< disable rejection of
                                                        non-standard preamble */
#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000 /**< enable transmit IPG */
#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000 /**< disable rejection of
                                                        FCS error */
#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000 /**< RX half duplex */
#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000 /**< enable RX checksum
                                                        offload */
#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000 /**< Do not copy pause
                                                        Frames to memory */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18	   /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000 /**< MDC Mask PCLK divisor */
#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000 /**< Discard FCS from
                                                        received frames */
#define XEMACPS_NWCFG_LENGTHERRDSCRD_MASK 0x00010000
/**< RX length error discard */
#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000 /**< RX buffer offset */
#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000 /**< Enable pause RX */
#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000 /**< Retry test */
#define XEMACPS_NWCFG_EXTADDRMATCHEN_MASK 0x00000200
/**< External address match enable */
#define XEMACPS_NWCFG_1000_MASK        0x00000400 /**< 1000 Mbps */
#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100 /**< Enable 1536 byte
                                                        frames reception */
#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080 /**< Receive unicast hash
                                                        frames */
#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040 /**< Receive multicast hash
                                                        frames */
#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020 /**< Do not receive
                                                        broadcast frames */
#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010 /**< Copy all frames */
#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008 /**< Jumbo frames */
#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004 /**< Receive only VLAN
                                                        frames */
#define XEMACPS_NWCFG_FDEN_MASK        0x00000002 /**< full duplex */
#define XEMACPS_NWCFG_100_MASK         0x00000001 /**< 100 Mbps */
/*@}*/

/** @name network status register bit definitaions
 * @{
 */
#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004 /**< PHY management idle */
#define XEMACPS_NWSR_MDIO_MASK         0x00000002 /**< Status of mdio_in */
/*@}*/


/** @name MAC address register word 1 mask
 * @{
 */
#define XEMACPS_LADDR_MACH_MASK        0x0000FFFF /**< Address bits[47:32]
                                                      bit[31:0] are in BOTTOM */
/*@}*/


/** @name DMA control register bit definitions
 * @{
 */
#define XEMACPS_DMACR_RXBUF_MASK      0x00FF0000 /**< Mask bit for RX buffer
                                                       size */
#define XEMACPS_DMACR_RXBUF_SHIFT     16	  /**< Shift bit for RX buffer
                                                       size */
#define XEMACPS_DMACR_TCPCKSUM_MASK   0x00000800 /**< enable/disable TX
                                                       checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK     0x00000400 /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK     0x00000300 /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK     0x00000080 /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK    0x0000001F /**< buffer burst length */
/*@}*/

/** @name transmit status register bit definitions
 * @{
 */
#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100 /**< Transmit hresp not OK */
#define XEMACPS_TXSR_URUN_MASK        0x00000040 /**< Transmit underrun */
#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020 /**< Transmit completed OK */
#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010 /**< Transmit buffs exhausted
                                                       mid frame */
#define XEMACPS_TXSR_TXGO_MASK        0x00000008 /**< Status of go flag */
#define XEMACPS_TXSR_RXOVR_MASK       0x00000004 /**< Retry limit exceeded */
#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002 /**< Collision tx frame */
#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001 /**< TX buffer used bit set */

#define XEMACPS_TXSR_ERROR_MASK      (XEMACPS_TXSR_HRESPNOK_MASK | \
                                       XEMACPS_TXSR_URUN_MASK | \
                                       XEMACPS_TXSR_BUFEXH_MASK | \
                                       XEMACPS_TXSR_RXOVR_MASK | \
                                       XEMACPS_TXSR_FRAMERX_MASK | \
                                       XEMACPS_TXSR_USEDREAD_MASK)
/*@}*/

/**
 * @name receive status register bit definitions
 * @{
 */
#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008 /**< Receive hresp not OK */
#define XEMACPS_RXSR_RXOVR_MASK       0x00000004 /**< Receive overrun */
#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002 /**< Frame received OK */
#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001 /**< RX buffer used bit set */

#define XEMACPS_RXSR_ERROR_MASK      (XEMACPS_RXSR_HRESPNOK_MASK | \
                                       XEMACPS_RXSR_RXOVR_MASK | \
                                       XEMACPS_RXSR_BUFFNA_MASK)
/*@}*/

/**
 * @name interrupts bit definitions
 * Bits definitions are same in XEMACPS_ISR_OFFSET,
 * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
 * @{
 */
#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000 /**< PTP Psync transmitted */
#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000 /**< PTP Pdelay_req
						     transmitted */
#define XEMACPS_IXR_PTPSTX_MASK     0x00800000 /**< PTP Sync transmitted */
#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000 /**< PTP Delay_req transmitted
						*/
#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000 /**< PTP Psync received */
#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000 /**< PTP Pdelay_req received */
#define XEMACPS_IXR_PTPSRX_MASK     0x00080000 /**< PTP Sync received */
#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000 /**< PTP Delay_req received */
#define XEMACPS_IXR_PAUSETX_MASK    0x00004000	/**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000	/**< Pause time has reached
                                                     zero */
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000	/**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800	/**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK      0x00000400	/**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080	/**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK      0x00000040	/**< Transmit err occurred or
                                                     no buffers*/
#define XEMACPS_IXR_RETRY_MASK      0x00000020	/**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK       0x00000010	/**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK     0x00000008	/**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK     0x00000004	/**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK    0x00000002	/**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK      0x00000001	/**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK        0x00007FFF	/**< Everything! */

#define XEMACPS_IXR_TX_ERR_MASK    (XEMACPS_IXR_TXEXH_MASK |         \
                                     XEMACPS_IXR_RETRY_MASK |         \
                                     XEMACPS_IXR_URUN_MASK  |         \
                                     XEMACPS_IXR_TXUSED_MASK)


#define XEMACPS_IXR_RX_ERR_MASK    (XEMACPS_IXR_HRESPNOK_MASK |      \
                                     XEMACPS_IXR_RXUSED_MASK |        \
                                     XEMACPS_IXR_RXOVR_MASK)

/*@}*/

/** @name PHY Maintenance bit definitions
 * @{
 */
#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000	/**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000	/**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000	/**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000	/**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000	/**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFF	/**< data bits */
#define XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK   23	/**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK   18	/**< Shift bits for PHREG */
/*@}*/

/* Transmit buffer descriptor status words offset
 * @{
 */
#define XEMACPS_BD_ADDR_OFFSET  0x00000000 /**< word 0/addr of BDs */
#define XEMACPS_BD_STAT_OFFSET  0x00000004 /**< word 1/status of BDs */
/*
 * @}
 */

/* Transmit buffer descriptor status words bit positions.
 * Transmit buffer descriptor consists of two 32-bit registers,
 * the first - word0 contains a 32-bit address pointing to the location of
 * the transmit data.
 * The following register - word1, consists of various information to control
 * the XEmacPs transmit process.  After transmit, this is updated with status
 * information, whether the frame was transmitted OK or why it had failed.
 * @{
 */
#define XEMACPS_TXBUF_USED_MASK  0x80000000 /**< Used bit. */
#define XEMACPS_TXBUF_WRAP_MASK  0x40000000 /**< Wrap bit, last descriptor */
#define XEMACPS_TXBUF_RETRY_MASK 0x20000000 /**< Retry limit exceeded */
#define XEMACPS_TXBUF_URUN_MASK  0x10000000 /**< Transmit underrun occurred */
#define XEMACPS_TXBUF_EXH_MASK   0x08000000 /**< Buffers exhausted */
#define XEMACPS_TXBUF_TCP_MASK   0x04000000 /**< Late collision. */
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000 /**< No CRC */
#define XEMACPS_TXBUF_LAST_MASK  0x00008000 /**< Last buffer */
#define XEMACPS_TXBUF_LEN_MASK   0x00003FFF /**< Mask for length field */
/*
 * @}
 */

/* Receive buffer descriptor status words bit positions.
 * Receive buffer descriptor consists of two 32-bit registers,
 * the first - word0 contains a 32-bit word aligned address pointing to the
 * address of the buffer. The lower two bits make up the wrap bit indicating
 * the last descriptor and the ownership bit to indicate it has been used by
 * the XEmacPs.
 * The following register - word1, contains status information regarding why
 * the frame was received (the filter match condition) as well as other
 * useful info.
 * @{
 */
#define XEMACPS_RXBUF_BCAST_MASK     0x80000000 /**< Broadcast frame */
#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000 /**< Multicast hashed frame */
#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000 /**< Unicast hashed frame */
#define XEMACPS_RXBUF_EXH_MASK       0x08000000 /**< buffer exhausted */
#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000 /**< Specific address
                                                      matched */
#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000 /**< Type ID matched */
#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000 /**< ID matched mask */
#define XEMACPS_RXBUF_VLAN_MASK      0x00200000 /**< VLAN tagged */
#define XEMACPS_RXBUF_PRI_MASK       0x00100000 /**< Priority tagged */
#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000 /**< Vlan priority */
#define XEMACPS_RXBUF_CFI_MASK       0x00010000 /**< CFI frame */
#define XEMACPS_RXBUF_EOF_MASK       0x00008000 /**< End of frame. */
#define XEMACPS_RXBUF_SOF_MASK       0x00004000 /**< Start of frame. */
#define XEMACPS_RXBUF_LEN_MASK       0x00003FFF /**< Mask for length field */

#define XEMACPS_RXBUF_WRAP_MASK      0x00000002 /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK       0x00000001 /**< Used bit.. */
#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFC /**< Mask for address */
/*
 * @}
 */

/*
 * Define appropriate I/O access method to mempry mapped I/O or other
 * intarfce if necessary.
 */

#define XEmacPs_In32  Xil_In32
#define XEmacPs_Out32 Xil_Out32


/****************************************************************************/
/**
*
* Read the given register.
*
* @param    BaseAddress is the base address of the device
* @param    RegOffset is the register offset to be read
*
* @return   The 32-bit value of the register
*
* @note
* C-style signature:
*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
    XEmacPs_In32((BaseAddress) + (RegOffset))


/****************************************************************************/
/**
*
* Write the given register.
*
* @param    BaseAddress is the base address of the device
* @param    RegOffset is the register offset to be written
* @param    Data is the 32-bit value to write to the register
*
* @return   None.
*
* @note
* C-style signature:
*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
*         u32 Data)
*
*****************************************************************************/
#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
    XEmacPs_Out32((BaseAddress) + (RegOffset), (Data))

#ifdef __cplusplus
  }
#endif

#endif /* end of protection macro */