system.par

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

Release 14.2 par P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

LENOVO-RCQ::  Mon Oct 08 09:12:58 2012

par -w -ol high system_map.ncd system.ncd system.pcf 


Constraints file: system.pcf.
Loading device for application Rf_Device from file '7z020.nph' in environment
C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.
   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)


Device speed data version:  "ADVANCED 1.02 2012-07-09".



Device Utilization Summary:

   Number of BUFGs                           1 out of 32      3%
   Number of External IOB33s                 8 out of 200     4%
      Number of LOCed IOB33s                 8 out of 8     100%

   Number of External IOPADs               130 out of 130   100%
      Number of LOCed IOPADs               127 out of 130    97%

   Number of OLOGICE2s                       8 out of 200     4%
   Number of PS7s                            1 out of 1     100%
   Number of Slices                         74 out of 13300   1%
   Number of Slice Registers               129 out of 106400  1%
      Number used as Flip Flops            129
      Number used as Latches                 0
      Number used as LatchThrus              0

   Number of Slice LUTS                    181 out of 53200   1%
   Number of Slice LUT-Flip Flop pairs     198 out of 53200   1%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx
   Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis.  REAL time: 16 secs 
Finished initial Timing Analysis.  REAL time: 16 secs 

Starting Router


Phase  1  : 2736 unrouted;      REAL time: 17 secs 

Phase  2  : 854 unrouted;      REAL time: 18 secs 

Phase  3  : 274 unrouted;      REAL time: 18 secs 

Phase  4  : 274 unrouted; (Setup:0, Hold:13, Component Switching Limit:0)     REAL time: 22 secs 

Updating file: system.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:27, Component Switching Limit:0)     REAL time: 22 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:27, Component Switching Limit:0)     REAL time: 22 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:27, Component Switching Limit:0)     REAL time: 22 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:27, Component Switching Limit:0)     REAL time: 22 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 22 secs 
Total REAL time to Router completion: 22 secs 
Total CPU time to Router completion: 22 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|processing_system7_0 |              |      |      |            |             |
|          _FCLK_CLK0 |BUFGCTRL_X0Y31| No   |   68 |  0.230     |  1.770      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     9.608ns|    10.392ns|       0|           0
  0" 50 MHz HIGH 50%                        | HOLD        |     0.004ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_axi_interconnect_1_reset_resync_ | SETUP       |         N/A|     1.092ns|     N/A|           0
  path" TIG                                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 24 secs 
Total CPU time to PAR completion: 24 secs 

Peak Memory Usage:  416 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file system.ncd



PAR done!