system_map.mrp

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

Release 14.2 Map P.28xd (nt)
Xilinx Mapping Report File for Design 'system'

Design Information
------------------
Command Line   : map -o system_map.ncd -w -pr b -ol high -timing -detail
system.ngd system.pcf 
Target Device  : xc7z020
Target Package : clg484
Target Speed   : -1
Mapper Version : zynq -- $Revision: 1.55 $
Mapped Date    : Mon Oct 08 09:12:13 2012

Design Summary
--------------
Number of errors:      0
Number of warnings:    6
Slice Logic Utilization:
  Number of Slice Registers:                   129 out of 106,400    1%
    Number used as Flip Flops:                 129
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        181 out of  53,200    1%
    Number used as logic:                      169 out of  53,200    1%
      Number using O6 output only:             146
      Number using O5 output only:               0
      Number using O5 and O6:                   23
      Number used as ROM:                        0
    Number used as Memory:                       8 out of  17,400    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             8
        Number using O6 output only:             8
        Number using O5 output only:             0
        Number using O5 and O6:                  0
    Number used exclusively as route-thrus:      4
      Number with same-slice register load:      4
      Number with same-slice carry load:         0
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                    74 out of  13,300    1%
  Number of LUT Flip Flop pairs used:          199
    Number with an unused Flip Flop:            78 out of     199   39%
    Number with an unused LUT:                  18 out of     199    9%
    Number of fully used LUT-FF pairs:         103 out of     199   51%
    Number of unique control sets:              14
    Number of slice register sites lost
      to control set restrictions:              47 out of 106,400    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                         8 out of     200    4%
    Number of LOCed IOBs:                        8 out of       8  100%
  Number of bonded IOPAD:                      130 out of     130  100%
    IOB Flip Flops:                              8

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                  0 out of     140    0%
  Number of RAMB18E1/FIFO18E1s:                  0 out of     280    0%
  Number of BUFG/BUFGCTRLs:                      1 out of      32    3%
    Number used as BUFGs:                        1
    Number used as BUFGCTRLs:                    0
  Number of IDELAYE2/IDELAYE2_FINEDELAYs:        0 out of     200    0%
  Number of ILOGICE2/ILOGICE3/ISERDESE2s:        0 out of     200    0%
  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0
  Number of OLOGICE2/OLOGICE3/OSERDESE2s:        8 out of     200    4%
    Number used as OLOGICE2s:                    8
    Number used as OLOGICE3s:                    0
    Number used as OSERDESE2s:                   0
  Number of PHASER_IN/PHASER_IN_PHYs:            0 out of      16    0%
  Number of PHASER_OUT/PHASER_OUT_PHYs:          0 out of      16    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHCEs:                             0 out of      72    0%
  Number of BUFRs:                               0 out of      16    0%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DNA_PORTs:                           0 out of       1    0%
  Number of DSP48E1s:                            0 out of     220    0%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         0 out of       4    0%
  Number of IN_FIFOs:                            0 out of      16    0%
  Number of MMCME2_ADVs:                         0 out of       4    0%
  Number of OUT_FIFOs:                           0 out of      16    0%
  Number of PHASER_REFs:                         0 out of       4    0%
  Number of PHY_CONTROLs:                        0 out of       4    0%
  Number of PLLE2_ADVs:                          0 out of       4    0%
  Number of PS7s:                                1 out of       1  100%
  Number of STARTUPs:                            0 out of       1    0%
  Number of XADCs:                               0 out of       1    0%

Average Fanout of Non-Clock Nets:                2.02

Peak Memory Usage:  518 MB
Total REAL time to MAP completion:  42 secs 
Total CPU time to MAP completion:   33 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB" has an undefined
   IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB" is not constrained
   (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK" has an undefined
   IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK" is not constrained
   (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB" has an undefined
   IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB" is not constrained
   (LOC) to a specific location.

Section 3 - Informational
-------------------------
INFO:Map:220 - The command line option -timing is automatically supported for
   this architecture. Therefore, it is not necessary to specify this option.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<11> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<10> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<9> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<8> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<7> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<6> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<5> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<4> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<3> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<2> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<1> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_WID<0> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_ARLOCK<1> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_AWLOCK<1> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<23> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<22> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<21> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<20> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<19> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<18> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<17> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<16> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<15> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<14> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<13> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<12> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<11> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<10> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<9> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WDATA<8> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_ARQOS<3> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_ARQOS<2> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_ARQOS<1> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_ARQOS<0> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_AWQOS<3> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_AWQOS<2> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_AWQOS<1> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_S_AWQOS<0> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WSTRB<3> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WSTRB<2> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WSTRB<1> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_WSTRB<0> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_ARADDR<8> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_ARADDR<7> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_ARADDR<6> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_ARADDR<5> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_ARADDR<4> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_ARADDR<1> has no load.
INFO:LIT:243 - Logical network axi_interconnect_1_M_ARADDR<0> has no load.
INFO:LIT:243 - Logical network N129 has no load.
INFO:LIT:243 - Logical network N130 has no load.
INFO:LIT:243 - Logical network N131 has no load.
INFO:LIT:243 - Logical network N132 has no load.
INFO:LIT:243 - Logical network N133 has no load.
INFO:LIT:243 - Logical network N134 has no load.
INFO:LIT:243 - Logical network N135 has no load.
INFO:LIT:243 - Logical network N136 has no load.
INFO:LIT:243 - Logical network N137 has no load.
INFO:LIT:243 - Logical network N138 has no load.
INFO:LIT:243 - Logical network N139 has no load.
INFO:LIT:243 - Logical network N140 has no load.
INFO:LIT:243 - Logical network N141 has no load.
INFO:LIT:243 - Logical network N142 has no load.
INFO:LIT:243 - Logical network N143 has no load.
INFO:LIT:243 - Logical network N144 has no load.
INFO:LIT:243 - Logical network N145 has no load.
INFO:LIT:243 - Logical network N146 has no load.
INFO:LIT:243 - Logical network N147 has no load.
INFO:LIT:243 - Logical network N148 has no load.
INFO:LIT:243 - Logical network N149 has no load.
INFO:LIT:243 - Logical network N150 has no load.
INFO:LIT:243 - Logical network N151 has no load.
INFO:LIT:243 - Logical network N152 has no load.
INFO:LIT:243 - Logical network N153 has no load.
INFO:LIT:243 - Logical network N154 has no load.
INFO:LIT:243 - Logical network N155 has no load.
INFO:LIT:243 - Logical network N156 has no load.
INFO:LIT:243 - Logical network N157 has no load.
INFO:LIT:243 - Logical network N158 has no load.
INFO:LIT:243 - Logical network N159 has no load.
INFO:LIT:243 - Logical network N160 has no load.
INFO:LIT:243 - Logical network N161 has no load.
INFO:LIT:243 - Logical network N162 has no load.
INFO:LIT:243 - Logical network N163 has no load.
INFO:LIT:243 - Logical network N164 has no load.
INFO:LIT:243 - Logical network N165 has no load.
INFO:LIT:243 - Logical network N166 has no load.
INFO:LIT:243 - Logical network N167 has no load.
INFO:LIT:243 - Logical network N168 has no load.
INFO:LIT:243 - Logical network N169 has no load.
INFO:LIT:243 - Logical network N170 has no load.
INFO:LIT:243 - Logical network N171 has no load.
INFO:LIT:243 - Logical network N172 has no load.
INFO:LIT:243 - Logical network N173 has no load.
INFO:LIT:243 - Logical network N174 has no load.
INFO:LIT:243 - Logical network N175 has no load.
INFO:LIT:243 - Logical network N176 has no load.
INFO:LIT:243 - Logical network N177 has no load.
INFO:LIT:243 - Logical network N178 has no load.
INFO:LIT:243 - Logical network N179 has no load.
INFO:LIT:243 - Logical network N180 has no load.
INFO:LIT:243 - Logical network N181 has no load.
INFO:LIT:243 - Logical network N182 has no load.
INFO:LIT:243 - Logical network N183 has no load.
INFO:LIT:243 - Logical network N184 has no load.
INFO:LIT:243 - Logical network N185 has no load.
INFO:LIT:243 - Logical network N186 has no load.
INFO:LIT:243 - Logical network N187 has no load.
INFO:LIT:243 - Logical network N188 has no load.
INFO:LIT:243 - Logical network N189 has no load.
INFO:LIT:243 - Logical network N190 has no load.
INFO:LIT:243 - Logical network N191 has no load.
INFO:LIT:243 - Logical network N192 has no load.
INFO:LIT:243 - Logical network N193 has no load.
INFO:LIT:243 - Logical network N194 has no load.
INFO:LIT:243 - Logical network N195 has no load.