system.pcf

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_35"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_34"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_33"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_32"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_31"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_30"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_29"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_28"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_15"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_14"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_11"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_10"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_9"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_8"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_7"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_6"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_5"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_4"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_3"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_2"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cnt_3"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cnt_2"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cnt_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cnt_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/write_cs_FSM_FFd1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/write_cs_FSM_FFd2"
        BEL
        "axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axilite.gen_axilite_conv.axilite_conv_inst/write_active"
        BEL
        "axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axilite.gen_axilite_conv.axilite_conv_inst/read_active"
        BEL
        "axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axilite.gen_axilite_conv.axilite_conv_inst/busy"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_grant_hot_i_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_valid_i"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/s_axi_rlast_i"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/s_axi_arready_i"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cs_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/s_axi_awready_i"
        BEL
        "axi_interconnect_1/axi_interconnect_1/mi_register_slice_bank/gen_reg_slot[0].register_slice_inst/reset"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/reset"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/s_ready_i_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/grant_rnw"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_aw/m_ready_d_2"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_aw/m_ready_d_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_aw/m_ready_d_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_ar/m_ready_d_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_ar/m_ready_d_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/m_atarget_enc_0_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/grant_rnw_1"
        BEL "axi_LDs/axi_LDs/ip2bus_data_i_D1_24" BEL
        "axi_LDs/axi_LDs/ip2bus_data_i_D1_25" BEL
        "axi_LDs/axi_LDs/ip2bus_data_i_D1_26" BEL
        "axi_LDs/axi_LDs/ip2bus_data_i_D1_27" BEL
        "axi_LDs/axi_LDs/ip2bus_data_i_D1_28" BEL
        "axi_LDs/axi_LDs/ip2bus_data_i_D1_29" BEL
        "axi_LDs/axi_LDs/ip2bus_data_i_D1_30" BEL
        "axi_LDs/axi_LDs/ip2bus_data_i_D1_31" BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd2"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_7"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_6"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_5"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_4"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_3"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_2"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_1"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_0"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_out_i_0"
        BEL "axi_LDs/axi_LDs/gpio_core_1/gpio_xferAck_Reg" BEL
        "axi_LDs/axi_LDs/gpio_core_1/iGPIO_xferAck" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_OE_0" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_OE_1" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_OE_2" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_OE_3" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_OE_4" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_OE_5" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_OE_6" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_OE_7" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_Out_0" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_Out_1" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_Out_2" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_Out_3" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_Out_4" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_Out_5" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_Out_6" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_Out_7" BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i"
        BEL "axi_LDs/axi_LDs/ip2bus_wrack_i_D1" BEL
        "axi_LDs/axi_LDs/ip2bus_rdack_i_D1" BEL "axi_LDs/axi_LDs/bus2ip_reset"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_3"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_2"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_1"
        BEL
        "axi_LDs/axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_0"
        BEL "axi_LDs/axi_LDs/gpio_core_1/GPIO_DBus_i_31" BEL
        "axi_LDs/axi_LDs/gpio_core_1/GPIO_DBus_i_30" BEL
        "axi_LDs/axi_LDs/gpio_core_1/GPIO_DBus_i_29" BEL
        "axi_LDs/axi_LDs/gpio_core_1/GPIO_DBus_i_28" BEL
        "axi_LDs/axi_LDs/gpio_core_1/GPIO_DBus_i_27" BEL
        "axi_LDs/axi_LDs/gpio_core_1/GPIO_DBus_i_26" BEL
        "axi_LDs/axi_LDs/gpio_core_1/GPIO_DBus_i_25" BEL
        "axi_LDs/axi_LDs/gpio_core_1/GPIO_DBus_i_24" BEL
        "axi_LDs/axi_LDs/gpio_core_1/Mshreg_gpio_Data_In_0" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_In_0" BEL
        "axi_LDs/axi_LDs/gpio_core_1/Mshreg_gpio_Data_In_1" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_In_1" BEL
        "axi_LDs/axi_LDs/gpio_core_1/Mshreg_gpio_Data_In_2" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_In_2" BEL
        "axi_LDs/axi_LDs/gpio_core_1/Mshreg_gpio_Data_In_3" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_In_3" BEL
        "axi_LDs/axi_LDs/gpio_core_1/Mshreg_gpio_Data_In_4" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_In_4" BEL
        "axi_LDs/axi_LDs/gpio_core_1/Mshreg_gpio_Data_In_5" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_In_5" BEL
        "axi_LDs/axi_LDs/gpio_core_1/Mshreg_gpio_Data_In_6" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_In_6" BEL
        "axi_LDs/axi_LDs/gpio_core_1/Mshreg_gpio_Data_In_7" BEL
        "axi_LDs/axi_LDs/gpio_core_1/gpio_Data_In_7" PIN
        "processing_system7_0/processing_system7_0/PS7_i_pins<357>";
TIMEGRP axi_interconnect_1_reset_resync = BEL
        "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2"
        BEL
        "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_0";
TIMEGRP axi_interconnect_1_reset_source = FFS(*) PADS(*);
PATH TS_axi_interconnect_1_reset_resync_path = FROM TIMEGRP
        "axi_interconnect_1_reset_source" TO TIMEGRP
        "axi_interconnect_1_reset_resync";
PATH "TS_axi_interconnect_1_reset_resync_path" TIG;
TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_0" 50 MHz HIGH 50%;
SCHEMATIC END;