system.twr

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

--------------------------------------------------------------------------------
Release 14.2 Trace  (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -e 3 -xml system.twx
system.ncd system.pcf

Design file:              system.ncd
Physical constraint file: system.pcf
Device,package,speed:     xc7z020,clg484,C,-1 (ADVANCED 1.02 2012-07-09)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: PATH "TS_axi_interconnect_1_reset_resync_path" TIG;

 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_0" 50 MHz HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 1680 paths analyzed, 640 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  10.392ns.
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.

Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 1682 paths, 0 nets, and 918 connections

Design statistics:
   Minimum period:  10.392ns   (Maximum frequency:  96.228MHz)


Analysis completed Mon Oct 08 09:13:40 2012 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 366 MB