system.bgn

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

Release 14.2 - Bitgen P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
PMSPEC -- Overriding Xilinx file <C:/Xilinx/14.2/ISE_DS/EDK/zynq/data/zynq.acd>
with local file <C:/Xilinx/14.2/ISE_DS/ISE/zynq/data/zynq.acd>
Loading device for application Rf_Device from file '7z020.nph' in environment
C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.
   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1
Opened constraints file system.pcf.

Mon Oct 08 09:13:57 2012

C:\Xilinx\14.2\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -w system.ncd 

Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable*              |
+----------------------+----------------------+
| StartupClk           | Cclk*                |
+----------------------+----------------------+
| DonePin              | Pullup*              |
+----------------------+----------------------+
| ProgPin              | Pullup*              |
+----------------------+----------------------+
| InitPin              | Pullup*              |
+----------------------+----------------------+
| TckPin               | Pullup*              |
+----------------------+----------------------+
| TdiPin               | Pullup*              |
+----------------------+----------------------+
| TdoPin               | Pullup*              |
+----------------------+----------------------+
| TmsPin               | Pullup*              |
+----------------------+----------------------+
| UnusedPin            | Pulldown*            |
+----------------------+----------------------+
| GWE_cycle            | 6*                   |
+----------------------+----------------------+
| GTS_cycle            | 5*                   |
+----------------------+----------------------+
| OverTempPowerDown    | Disable*             |
+----------------------+----------------------+
| LCK_cycle            | NoWait*              |
+----------------------+----------------------+
| Match_cycle          | NoWait               |
+----------------------+----------------------+
| DONE_cycle           | 4*                   |
+----------------------+----------------------+
| DonePipe             | Yes*                 |
+----------------------+----------------------+
| Security             | None*                |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF*          |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| DCIUpdateMode        | AsRequired*          |
+----------------------+----------------------+
| ICAP_Select          | Auto*                |
+----------------------+----------------------+
| InitSignalsError     | Enable*              |
+----------------------+----------------------+
| XADCPartialReconfig  | Disable*             |
+----------------------+----------------------+
| XADCEnhancedLinearity | Off*                 |
+----------------------+----------------------+
| JTAG_XADC            | Enable*              |
+----------------------+----------------------+
| Disable_JTAG         | No*                  |
+----------------------+----------------------+
| XADCPowerDown        | Disable*             |
+----------------------+----------------------+
| Partial              | (Not Specified)*     |
+----------------------+----------------------+
| USR_ACCESS           | None*                |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No*                  |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

There were 0 CONFIG constraint(s) processed from system.pcf.


Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.