spihardware.h

一个基于windows mobile 的GPS 接受IC 驱动程序。

#ifndef SPI_HARDWARE_H__          // {
#define SPI_HARDWARE_H__

//----------------------------------------------------
//      Handy bit field definitions
//----------------------------------------------------
#ifdef  BIT
#undef  BIT
#endif
#define BIT(p)      (1L << (p))

#ifdef  MASK
#undef  MASK
#endif
#define MASK(nBits,shift)   ((BIT(nBits+1) - 1) << (shift))

#include "clockHardware.h"

namespace SSP {

//------------------------------------------------------------------------
//      Synchronous Serial Port Structure - see page 8-54
//------------------------------------------------------------------------

struct XLLP_SSP_REGS
{
    DWORD cr0;        // control register 0
    DWORD cr1;        // control register 1
    DWORD sr;         // status register
    DWORD itr;        // interrupt test register
    DWORD dr;         // data read/write register
    DWORD reserved[5];// Addresses 0x14 to 0x24 are empty.
    DWORD to;         // timeout register
    DWORD psp;        // programmable serial protocol register
    DWORD tsa;        // TX timeslot active register
    DWORD rsa;        // RX timeslot active register
    DWORD acd;        // audio clock divider register
};

#define BULVERDE_BASE_REG_PA_SSP3 0x41900000

//-------------------------------------------------------------------
//      Control Register 0 - see Table 8-6 on page 8-25
//-------------------------------------------------------------------

namespace CR0 {

#define CR0_DSS(p)      (((p)      ) &  DSS_MASK)
#define CR0_FRF(p)      (((p) <<  4) &  FRF_MASK)
#define CR0_SCR(p)      (((p) <<  8) &  SCR_MASK)
#define CR0_FRDC(p)     (((p) << 27) & FRDC_MASK)

    enum
    {
        DSS_MASK    = MASK(4,0),
        DSS_8BIT    = CR0_DSS(0x7),
        FRF_MASK    = MASK(2,4),
        FRF_SPI     = CR0_FRF(0),      // 0=spi, 1=TI, 2=uWire, 3=PSP
        ECS         = BIT(6),
        SSE         = BIT(7),
        SCR_MASK    = MASK(12,8),
        SCR_128K    = CR0_SCR(0x67),
        SCR_512K    = CR0_SCR(0x19),    // Assuming a 13MHz clock
        EDSS        = BIT(20),
        NCS         = BIT(21),
        RIM         = BIT(22),
        TIM         = BIT(23),
        FRDC_MASK   = MASK(3,24),
        res_MASK    = MASK(3,27),
        ACS         = BIT(30),
        MOD         = BIT(31)
    };

}       // namespace CR0


//-------------------------------------------------------------------
//      Control Register 1 - see Table 8-7 on page 8-29
//-------------------------------------------------------------------

namespace CR1 {

#define CR1_TFT(p)     (((p) <<  8) & TFT_MASK)
#define CR1_RFT(p)     (((p) << 27) & RFT_MASK)

    enum
    {
        RIE         = BIT(0),
        TIE         = BIT(1),
        LBM         = BIT(2),
        SPO         = BIT(3),
        SPH         = BIT(4),
        MWDA        = BIT(5),
        TFT_MASK    = MASK(4,6),
        RFT_MASK    = MASK(4,10),
        RFT_8       = CR1_RFT(8),      // Read threshold is 8 bytes.
        EFWR        = BIT(14),
        STRF        = BIT(15),
        IFS         = BIT(16),
        res         = BIT(17),
        PINTE       = BIT(18),
        TINTE       = BIT(19),
        RSRE        = BIT(20),
        TSRE        = BIT(21),
        TRAIL       = BIT(22),
        RWOT        = BIT(23),
        SFRMDIR     = BIT(24),
        SCLKDIR     = BIT(25),
        ECRB        = BIT(26),
        ECRA        = BIT(27),
        SCFR        = BIT(28),
        EBCEI       = BIT(29),
        TTE         = BIT(30),
        TTELP       = BIT(31)
    };

}       // namespace CR0


//-------------------------------------------------------------------
//      Status Register - see Table 8-11 on page 8-43
//-------------------------------------------------------------------

namespace SR {

    enum
    {
        res0        = MASK(2,0),
        TNF         = BIT(2),
        RNE         = BIT(3),
        BSY         = BIT(4),
        TFS         = BIT(5),
        RFS         = BIT(6),
        ROR         = BIT(7),
        TFL_SHIFT   = 8,
        TFL_MASK    = MASK(4,TFL_SHIFT),
        RFL_SHIFT   = 12,
        RFL_MASK    = MASK(4,RFL_SHIFT),
        res16       = MASK(2,16),
        PINT        = BIT(18),
        TINT        = BIT(19),
        EOC         = BIT(20),
        TUR         = BIT(21),
        CSS         = BIT(22),
        BCE         = BIT(23),
        res24       = MASK(8,24)
    };

#define TFL(p)     (((p) & SR::TFL_MASK) >> SR::TFL_SHIFT) 
#define RFL(p)     (((p) & SR::RFL_MASK) >> SR::RFL_SHIFT) 

}       // namespace SR

}       // namespace SSP

//-----------------------------------------------------------------------------
//  global variable - the pointer to the SPI hardware.
//  This is the connection between the SPI_xxx() routines and the
//  cust_hw_spi.h macros.
//-----------------------------------------------------------------------------

struct SSP::XLLP_SSP_REGS;
extern volatile SSP::XLLP_SSP_REGS* gpSsp3hw;

//-------------------------------------------------------------------------
//      SSP Configuration - make it an SPI port.
//-------------------------------------------------------------------------

inline void
sspInit(volatile SSP::XLLP_SSP_REGS& hw)
{
	using namespace SSP;
	hw.cr0   =   CR0::DSS_8BIT
            |    CR0::SCR_128K
            |    CR0::RIM
            |    CR0::TIM;			// | CR0::FRF_SPI;
	hw.cr0  &= ~(CR0::EDSS | CR0::NCS | CR0::ECS);

    // For Motorola SPI initialization, set:
    //      CR1::SPH=0
    //      CR1::SPO=0
	hw.cr1   = 0;
	// hw.cr1   = (CR1::SCFR | CR1::PINTE);

	hw.itr   = 0;
	hw.to    = 0x1000;      // 4096 clock timeout?
}

#endif // SPI_HARDWARE_H__   }