📄 lcd_hw.h
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/*****************************************************************************
* Copyright Statement:
* --------------------
* This software is protected by Copyright and the information contained
* herein is confidential. The software may not be copied and the information
* contained herein may not be used or disclosed except with the written
* permission of MediaTek Inc. (C) 2001
*
*****************************************************************************/
/*****************************************************************************
*
* Filename:
* ---------
* lcd_hw.h
*
* Project:
* --------
* Maui_Software
*
* Description:
* ------------
* This file is intends for LCD driver.
*
* Author:
* -------
* -------
*
*============================================================================
* HISTORY
* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*------------------------------------------------------------------------------
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* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*============================================================================
****************************************************************************/
#ifndef _LCD_HW_H
#define _LCD_HW_H
/******************/
/* Main LCD Parameter */
/******************/
/* BEGIN 2005-03-15 TCL-xjinming added for GD85-2 LCD_MAIN..... */
/* RENESAS HD66791 ***********************************************************/
/* 128x160(64K/262), Parallel i/o, COG Type */
/***************************************************************************/
#if (defined(__GD85_2_TCL_DRV_LCD_RENESAS_HD66791__))
#define INDEX_R00H 0x0000
#define START_OSC 0x0001
#define STOP_OSC 0x0000
#define INDEX_R01H 0x0001
#define DRIVER_OUTPUT_CTRL1_D 0x0515
#define INDEX_R02H 0x0002
#define DRIVER_AC_CTRL_D 0x0700
#define INDEX_R03H 0x0003
#define ENTRY_MODE_D 0x1030
#define INDEX_R07H 0x0007
/*set display on sequence*/
#define DISPLAY_D0 0x0000
#define DISPLAY_D1 0x0005
#define DISPLAY_D2 0x0025
#define DISPLAY_D3 0x0027
#define DISPLAY_D4 0x0037
#define DISPLAYOFF_D0 0x0036
#define DISPLAYOFF_D1 0x0026
#define DISPLAYOFF_D2 0x0004
#define INDEX_R08H 0x0008
#define DISP_CTRL2_D 0x0808
#define INDEX_R09H 0x0009
#define DISP_CTRL3_D 0x0000
#define INDEX_R0BH 0x000B
#define FRAME_CYCLE_D 0x0008
#define INDEX_R0CH 0x000C
#define EXT_DISP_CTRL1_D 0x0000
#define INDEX_R0DH 0x000D
#define DRIVER_OUTPUT_CTRL2_D 0x444a
#define INDEX_R0EH 0x000E
#define EXT_DISP_CTRL2_D 0x0000
#define INDEX_R10H 0x0010
#define PWR_CTRL1_D1 0x0004
#define PWR_CTRL1_D2 0x0044
#define PWR_CTRL1_D3 0x0760
#define PWR_CTRL1_D4 0x6760
#define PWR_CTRL1_D5 0x0700
#define PWR_CTRL1_D6 0x0701
#define PWR_CTRL1_D7 0x0702
#define INDEX_R11H 0x0011
#define PWR_CTRL2_D1 0x0000
#define PWR_CTRL2_D2 0x0a12
#define INDEX_R12H 0x0012
#define PWR_CTRL3_D0 0x0000
#define PWR_CTRL3_D1 0x000e
#define PWR_CTRL3_D2 0x001e
#define INDEX_R13H 0x0013
#define PWR_CTRL4_D0 0x0000
#define PWR_CTRL4_D1 0x0e0f
#define PWR_CTRL4_D2 0x2d0f
#define INDEX_R15H 0x0015
#define GRAY_CTRL_D 0x0002
#define INDEX_R21H 0x0021
#define RAM_ADDR_D 0x0000
#define INDEX_R22H 0x0022
#define INDEX_R23H 0x0023
#define RAM_DATA_MASK1 0x0000
#define INDEX_R24H 0x0024
#define RAM_DATA_MASK2 0x0000
#define INDEX_R30H 0x0030
#define PKP0 0x0100
#define INDEX_R31H 0x0031
#define PKP1 0x0507
#define INDEX_R32H 0x0032
#define PKP2 0x0003
#define INDEX_R33H 0x0033
#define PKP3 0x0604
#define INDEX_R34H 0x0034
#define PKP4 0x0407
#define INDEX_R35H 0x0035
#define PKP5 0x0002
#define INDEX_R36H 0x0036
#define PKP6 0x0706
#define INDEX_R37H 0x0037
#define PKP7 0x0406
#define INDEX_R38H 0x0038
#define PKP8 0x0008
#define INDEX_R39H 0x0039
#define PKP9 0x0008
#define INDEX_R40H 0x0040
#define GATE_SCAN_POS_D 0x0001
#define INDEX_R41H 0x0041
#define VER_SCR_CTRL_D1 0x0000
#define INDEX_R42H 0x0042
#define FIRST_SCR_D 0x9f00
#define INDEX_R43H 0x0043
#define SECOND_SCR_D 0xafaf
#define INDEX_R44H 0x0044
#define HOR_RAM_ADDR_D 0x7f00
#define INDEX_R45H 0x0045
#define VER_RAM_ADDR_D 0x9f00
#define INDEX_R7EH 0x007e
#define WRITE_CLOCK_D 0x0010
#endif //#if (defined(__GD85_2_TCL_DRV_LCD_RENESAS_HD66791__))
/* END 2005-03-15 TCL-xjinming added for GD85-2 LCD_MAIN..... */
/* Epson D15G17E ***********************************************************/
/* 128x128(65K), Parallel i/o, COG Type */
/***************************************************************************/
#if (defined (__GD85_TCL_DRV_LCD_D15G17E_EPSON_1__) || defined (__GD85_TCL_DRV_LCD_D15G17E_EPSON_2__))
/* ENTER/EXIT Sleep Mode */
#define LCD_EXIT_SLEEP_D15G17E 0x11
#define LCD_ENTER_SLEEP_D15G17E 0x10
/* Display ON/OFF */
#define LCD_DISPLAY_OFF_D15G17E 0x28
#define LCD_DISPLAY_ON_D15G17E 0x29
#define LCD_PARTIAL_DISPLAY_OFF_D15G17E 0x13
#define LCD_PARTIAL_DISPLAY_ON_D15G17E 0x12
// Start of Display Control
#define LCD_DISPLAY_CTRL_SET_D15G17E 0xB6
/* Set Bias */
#define LCD_BIAS_SET_D15G17E 0x22
#define LCD_BIAS_VAL_D15G17E 0x22
/* Set Contrast */
#define LCD_CONTRAST_SET_D15G17E 0x25
#define LCD_CONTRAST_VAL_D15G17E 0x5B /* 0~127, 0x00~0x7F */
/* Set N-line Inversion Register */
#define LCD_NLINE_INVERSION_SET_D15G17E 0x34
#define LCD_NLINE_INVERSION_VAL_D15G17E 0x05
/* Set Temperature Compensation */
#define LCD_TEMP_COMPENSATION_SET_D15G17E 0xB7
#define LCD_TEMP_COMPENSATION_VAL_D15G17E 0x03
// End of Display Control
/* Set X/Y Address Area */
#define LCD_PAGE_ADDRESS_SET_D15G17E 0x2B
#define LCD_COLUMN_ADDRESS_SET_D15G17E 0x2A
/* Set Oscillator */
#define LCD_OSC_SET_D15G17E 0x02
#define LCD_OSC_VAL_D15G17E 0x00
/* Set DC-DC CLK Division */
#define LCD_DC2DC_SET_D15G17E 0x20
#define LCD_DC2DC_VAL_D15G17E 0x00
/* Set DC-DC Selection*/
#define LCD_DC2DC_CLK_DIV_SET_D15G17E 0x24
#define LCD_DC2DC_CLK_DIV_VAL_D15G17E 0x22
/* Set DC-DC AMP */
#define LCD_DC2DC_AMP_SET_D15G17E 0x26
#define LCD_DC2DC_AMP_VAL_D15G17E 0x00
/* Set Driver Output Mode */
#define LCD_DRIVER_OUTPUT_MODE_SET_D15G17E 0x10
#define LCD_DRIVER_OUTPUT_MODE_VAL_D15G17E4 0x00
/* Set Memory Entry Mode */
#define LCD_ENTRY_MODE_SET_D15G17E 0x40
#define LCD_ENTRY_MODE_VAL_D15G17E 0x00
/* Set Partial Display Mode */
#define LCD_DISPLAY_PATTERN_SET_D15G17E 0x53
#define LCD_DISPLAY_PATTERN_VAL_D15G17E 0x00
#define LCD_PARTIAL_DISPLAY_MODE_SET_D15G17E 0x55
#define LCD_PARTIAL_DISPLAY_MODE_VAL_D15G17E 0x00
#define LCD_PARTIAL_DISPLAY_STR_LINE_D15G17E 0x56
#define LCD_PARTIAL_DISPLAY_END_LINE_D15G17E 0x57
#define LCD_PARTIAL_DISPLAY_STR_VAL_D15G17E 0x00
#define LCD_PARTIAL_DISPLAY_END_VAL_D15G17E 0x83
/* Set Scroll Area */
#define LCD_SCROLL_MODE_SET_D15G17E 0x59
#define LCD_SCROLL_MODE_VAL_D15G17E 0x00
#define LCD_SCROLL_FIX_LINE_D15G17E 0x00
#define LCD_SCROLL_START_LINE_SET_D15G17E 0x5A
#define LCD_SCROLL_START_LINE_VAL_D15G17E 0x00
/* Software Reset */
#define LCD_SW_RESET_D15G17E 0x01
/* Write to RAM */
#define LCD_RAM_WRITE_D15G17E 0x2C
/**********/
/* Others */
/**********/
/* SHL Select */
#define LCD_COM_NORMAL_D15G17E 0xC0 /* COM0 △ COM63 */
#define LCD_COM_REVERSE_D15G17E 0xCF /* COM63 △ COM0 */
/* ADC Select */
#define LCD_SEG_NORMAL_D15G17E 0xA0 /* SEG0 △ SEG63 */
#define LCD_SEG_REVERSE_D15G17E 0xA1 /* SEG63 △ SEG0 */
/* Set Data Direction */
#define LCD_DATA_DIRECTION_D15G17E 0xE8
#define LCD_NOP_D15G17E 0xAA
#endif //#if (defined (__GD85_TCL_DRV_LCD_D15G17E_EPSON_1__) || defined (__GD85_TCL_DRV_LCD_D15G17E_EPSON_2__))
/* SAMSUNG S6B33B0A ***********************************************************/
/* 128x128(65K), Parallel i/o, COG Type */
/***************************************************************************/
#if (defined (__GD85_TCL_DRV_LCD_S6B33B0A_SAMSUNG__))
#define LCD_NOP_S6B33B0A 0x00
#define LCD_OSC_MODE_SET_S6B33B0A 0x02
#define LCD_DRIVER_OUTPUT_MODE_SET_S6B33B0A 0x10
#define LCD_DC2DC_SELECT_S6B33B0A 0x20
#define LCD_BIAS_SET_S6B33B0A 0x22
#define LCD_DC2DC_CLK_DIV_SET_S6B33B0A 0x24
#define LCD_DC2DC_AMP_SET_S6B33B0A 0x26
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