📄 lcd_sw.h

📁 MTK平台的多种LCD驱动
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/*****************************************************************************
*  Copyright Statement:
*  --------------------
*  This software is protected by Copyright and the information contained
*  herein is confidential. The software may not be copied and the information
*  contained herein may not be used or disclosed except with the written
*  permission of MediaTek Inc. (C) 2001
*
*****************************************************************************/

/*****************************************************************************
 *
 * Filename:
 * ---------
 *    lcd_sw.h
 *
 * Project:
 * --------
 *   Maui_Software
 *
 * Description:
 * ------------
 *   This file is intends for LCD driver.
 *
 * Author:
 * -------
 * -------
 *
 *============================================================================
 *             HISTORY
 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *------------------------------------------------------------------------------
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 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *============================================================================
 ****************************************************************************/
#include "lcd_if.h"

#ifndef _LCD_SW_H
#define _LCD_SW_H

//#define LCD16BitMode/*mao add*/
#define D15G17E_8BIT// by arthur for test



#if ( (defined(MT6208)) || (defined(FPGA)) || (defined(MT6205B)) )
   #define LCD_DUMMYADDR   0x80170010
   #ifdef ORDNANCE
      #define LCD_CTRLAddr		(0x20000000)
      #define LCD_DATAAddr		(0x2fffffff)
   #else /*!ORDNANCE*/
      #define LCD_CTRLAddr		(0x30000000)
      #define LCD_DATAAddr		(0x3fffffff)
   #endif   /*!ORDNANCE*/
#endif   /*(MT6208,FPGA,MT6205B)*/
#if ( (defined(MT6218)) )
   #define LCD_CTRLAddr		(0x28000000)
   #define LCD_DATAAddr		(0x2fffffff)
#endif      /*(MT6218)*/

#if (defined(MT6218B) || defined(MT6219)|| defined(MT6217))//20050413 yguangyong added 6217 option
//	#define LCD_CMD_DMA_MODE
	#define LCD_DUMMYADDR   		0x90000000
	
	/* BEGIN 2005-03-15 TCL-xjinming added for GD85-2 LCD_MAIN..... */
   #if (defined (__GD85_2_TCL_DRV_LCD_RENESAS_HD66791__))
	
   #define LCD_HD66791_CTRL_ADDR	   	LCD_PARALLEL0_A0_LOW_ADDR
   #define LCD_HD66791_DATA_ADDR	   	LCD_PARALLEL0_A0_HIGH_ADDR
   #define MAIN_LCD_CMD_ADDR		   	LCD_HD66791_CTRL_ADDR
   #define MAIN_LCD_DATA_ADDR		   	LCD_HD66791_DATA_ADDR
   #define MAIN_LCD_OUTPUT_FORMAT	   	LCM_8BIT_16_BPP_RGB565_1//output format RGB(565)

	#endif //#if (defined (__GD85_2_TCL_DRV_LCD_RENESAS_HD66791__))
/* END 2005-03-15 TCL-xjinming added for GD85-2 LCD_MAIN..... */		


   #if (defined (__GD85_1_TCL_DRV_LCD_S6D0123_HITACHI__))
   #define LCD_S6D0123_CTRL_ADDR	   	LCD_PARALLEL0_A0_LOW_ADDR
   #define LCD_S6D0123_DATA_ADDR	   	LCD_PARALLEL0_A0_HIGH_ADDR
   #define MAIN_LCD_CMD_ADDR		   		LCD_S6D0123_CTRL_ADDR
   #define MAIN_LCD_DATA_ADDR		   		LCD_S6D0123_DATA_ADDR
#ifdef LCD16BitMode	/*mao add*/
	#define MAIN_LCD_OUTPUT_FORMAT	   	LCM_16BIT_16_BPP_RGB565_1
#else
   #define MAIN_LCD_OUTPUT_FORMAT	   	LCM_8BIT_16_BPP_RGB565_1
#endif
	#endif //#if (defined (__GD85_1_TCL_DRV_LCD_S6D0123_HITACHI__))

	
	#if ( (defined(__GD85_TCL_DRV_LCD_D15G17E_EPSON_1__)) || (defined(__GD85_TCL_DRV_LCD_D15G17E_EPSON_2__)))
   #define LCD_D15G17E_CTRL_ADDR	   LCD_PARALLEL0_A0_LOW_ADDR
   #define LCD_D15G17E_DATA_ADDR	   LCD_PARALLEL0_A0_HIGH_ADDR
   #define MAIN_LCD_CMD_ADDR		   LCD_D15G17E_CTRL_ADDR
   #define MAIN_LCD_DATA_ADDR		   LCD_D15G17E_DATA_ADDR
   #define MAIN_LCD_OUTPUT_FORMAT	   LCM_8BIT_16_BPP_RGB565_1
	#endif //#if ( (defined(__GD85_TCL_DRV_LCD_D15G17E_EPSON_1__)) || (defined(__GD85_TCL_DRV_LCD_D15G17E_EPSON_2__)))

	#if (defined(__GD85_TCL_DRV_LCD_S6B33B0A_SAMSUNG__))
   #define LCD_S6B33B0A_CTRL_ADDR	   LCD_PARALLEL0_A0_LOW_ADDR
   #define LCD_S6B33B0A_DATA_ADDR	   LCD_PARALLEL0_A0_HIGH_ADDR
   #define MAIN_LCD_CMD_ADDR			   LCD_S6B33B0A_CTRL_ADDR
   #define MAIN_LCD_DATA_ADDR			   LCD_S6B33B0A_DATA_ADDR
   #define MAIN_LCD_OUTPUT_FORMAT	   LCM_8BIT_16_BPP_RGB565_1
	#endif //  #if (defined(__GD85_TCL_DRV_LCD_S6B33B0A_SAMSUNG__))
	
 
   #if (defined(__GD85_TCL_DRV_LCD_S1D15G27_WINTEK__) || defined(__GD85_TCL_DRV_LCD_S1D15G27_TRULY__))      //add by xjinming 20050707
   #define LCD_S1D15G27_CTRL_ADDR	   LCD_PARALLEL0_A0_LOW_ADDR
   #define LCD_S1D15G27_DATA_ADDR	   LCD_PARALLEL0_A0_HIGH_ADDR
   #define MAIN_LCD_CMD_ADDR		   LCD_S1D15G27_CTRL_ADDR
   #define MAIN_LCD_DATA_ADDR		   LCD_S1D15G27_DATA_ADDR
   #define MAIN_LCD_OUTPUT_FORMAT	   LCM_8BIT_16_BPP_RGB565_1	
   #endif    //#if (defined(__GD85_TCL_DRV_LCD_S1D15G27_WINTEK__))
	
 
/* BEGIN 2005-03-15 TCL-xjinming added for GD85-2 LCD_SUB..... */
	#if (defined (__GD85_2_TCL_DRV_LCD_L1F10289_EPSON__))
   #define LCD_L1F10289_CTRL_ADDR		LCD_PARALLEL1_A0_LOW_ADDR
	 #define LCD_L1F10289_DATA_ADDR		LCD_PARALLEL1_A0_HIGH_ADDR
	 #define SUB_LCD_CMD_ADDR		LCD_L1F10289_CTRL_ADDR
	 #define SUB_LCD_DATA_ADDR		LCD_L1F10289_DATA_ADDR
	 #define SUB_LCD_OUTPUT_FORMAT		LCM_8BIT_16_BPP_RGB565_1
	#endif //#if (defined (__GD85_2_TCL_DRV_LCD_L1F10289_EPSON__)) 
/* END 2005-03-15 TCL-xjinming added for GD85-2 LCD_MAIN..... */	
	
	//#ifdef __GD85_TCL_DRV_LCD_ST7565_SAMSUNG__   //modified by xjinming for TRULY LCD
	#if (defined(__GD85_TCL_DRV_LCD_ST7565_LINDA__) || defined(__GD85_TCL_DRV_LCD_ST7565_TRULY__))
   #define LCD_ST7565_CTRL_ADDR		   LCD_SERIAL0_A0_LOW_ADDR
   #define LCD_ST7565_DATA_ADDR		   LCD_SERIAL0_A0_HIGH_ADDR
   #define SUB_LCD_CMD_ADDR		       LCD_ST7565_CTRL_ADDR
   #define SUB_LCD_DATA_ADDR		   LCD_ST7565_DATA_ADDR
   #define SUB_LCD_OUTPUT_FORMAT	   LCM_8BIT_12_BPP_RGB444_1
	#endif //	#if (defined(__GD85_TCL_DRV_LCD_ST7565_LINDA__) || defined(__GD85_TCL_DRV_LCD_ST7565_TRULY__))
	
	#if (defined( __GD85_2_TCL_DRV_LCD_S6B33B2_LINDA__))
	#if defined(MBK_MB2X68B)				// CharlesWu added
	 #define LCD_S6B33B2_CTRL_ADDR	   	LCD_PARALLEL0_A0_LOW_ADDR //LCD_PARALLEL1_A0_LOW_ADDR // CharlesWu
	 #define LCD_S6B33B2_DATA_ADDR	   	LCD_PARALLEL0_A0_HIGH_ADDR //LCD_PARALLEL1_A0_HIGH_ADDR // CharlesWu
	#else	/* MBK_MB2X68B */
	 #define LCD_S6B33B2_CTRL_ADDR	   	LCD_PARALLEL1_A0_LOW_ADDR
   	 #define LCD_S6B33B2_DATA_ADDR	   	LCD_PARALLEL1_A0_HIGH_ADDR
	#endif	/* MBK_MB2X68B */
   #define SUB_LCD_CMD_ADDR		   			LCD_S6B33B2_CTRL_ADDR
   #define SUB_LCD_DATA_ADDR		   		LCD_S6B33B2_DATA_ADDR
   #define SUB_LCD_OUTPUT_FORMAT	   	LCM_8BIT_16_BPP_RGB565_1
	#endif  //#if (defined( __GD85_2_TCL_DRV_LCD_S6B33B2_LINDA__))
	
	#if (defined (__GD85_1_TCL_DRV_LCD_SH1101A_RITDISPLAY__))
	#if defined(MBK_MB2X68B)				// CharlesWu added
	 #define LCD_SH1101A_CTRL_ADDR	   	LCD_PARALLEL0_A0_LOW_ADDR //LCD_PARALLEL1_A0_LOW_ADDR // CharlesWu
	 #define LCD_SH1101A_DATA_ADDR	   	LCD_PARALLEL0_A0_HIGH_ADDR //LCD_PARALLEL1_A0_HIGH_ADDR // CharlesWu
	#else	/* MBK_MB2X68B */
	 #define LCD_SH1101A_CTRL_ADDR	   	LCD_PARALLEL1_A0_LOW_ADDR
   	 #define LCD_SH1101A_DATA_ADDR	   	LCD_PARALLEL1_A0_HIGH_ADDR
	#endif	/* MBK_MB2X68B */
   #define SUB_LCD_CMD_ADDR		   			LCD_SH1101A_CTRL_ADDR
   #define SUB_LCD_DATA_ADDR		   		LCD_SH1101A_DATA_ADDR
   #define SUB_LCD_OUTPUT_FORMAT	   	LCM_8BIT_12_BPP_RGB444_1
	
	#endif  //#if (defined (__GD85_1_TCL_DRV_LCD_SH1101A_RITDISPLAY__))


#endif /* (MT6205B, MT6218), (MT6218B,MT6219) */




/*************************************************************/
/* Main Macro                                                */
/*************************************************************/
/*************************************************************/
/* RENESAS Main HD66791,64k/262k Color, 128x160 Parallel(TFT)*/
/*************************************************************/
/* BEGIN 2005-03-15 TCL-xjinming added for GD85-2 LCD_MAIN..... */
#if (defined (__GD85_2_TCL_DRV_LCD_RENESAS_HD66791__))
#if ((defined(MT6208)) || (defined(MT6218)) ||(defined(MT6205B))||(defined(MT6218B))||(defined(MT6217))) //20050415 yguangyong added 6217

   #ifdef MCU_13M
      #define LCD_delay_HD66791()
   #endif	/* MCU_13M */
   
   #ifdef MCU_26M
      #define LCD_delay_HD66791()\
         {\
         	kal_uint16  _stat;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         }
   #endif	/* MCU_26M */
   
   #ifdef MCU_39M
      #define LCD_delay_HD66791()\
         {\
         	kal_uint16  _stat;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         }
   #endif	/* MCU_39M */

   #ifdef MCU_52M
      #define LCD_delay_HD66791()\
         {\
         	kal_uint16  _stat;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         }
      #ifdef DUAL_LCD
			#define LCD_delay_ST7565() \
			{\
				kal_uint16  _stat;\
				_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
				_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
				_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
				_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
			}
      #endif   
   #endif	/* MCU_52M */

#endif	/* MT6208 */


#if (defined(MT6218B) || defined(MT6219)|| defined(MT6217)) //20050415 yguangyong added 6217
	#ifdef LCD_CMD_DMA_MODE
		#define LCD_SEND_DMA_CMD(n) \
			{\
			DISABLE_LCD_TRANSFER_COMPLETE_INT;\
			SET_LCD_ROI_CTRL_NUMBER_OF_CMD(n);\
			ENABLE_LCD_ROI_CTRL_CMD_FIRST;\
			SET_LCD_ROI_WINDOW_SIZE(0,0);\
			START_LCD_TRANSFER;\
			while (LCD_IS_RUNNING) {};\
			}

			#define LCD_CtrlWrite_HD66791(_data) \
			{\
				SET_LCD_CMD_PARAMETER(0,LCD_CMD,(_data & 0xFF00 )>>8);\
				SET_LCD_CMD_PARAMETER(1,LCD_CMD,(_data & 0xFF));\
				LCD_SEND_DMA_CMD(2);\
			}

			#define LCD_DataWrite_HD66791(_data) \
			{\
        SET_LCD_CMD_PARAMETER(0,LCD_DATA,(_data & 0xFF00)>>8);\
        SET_LCD_CMD_PARAMETER(1,LCD_DATA, (_data & 0xFF));\
				LCD_SEND_DMA_CMD(2);\
			}

	#else
			#define LCD_CtrlWrite_HD66791(_data) \
			{ \
				*(volatile kal_uint8 *)LCD_HD66791_CTRL_ADDR = ((_data & 0xFF00) >>8);\
				LCD_delay_HD66791(); \
				*(volatile kal_uint8 *)LCD_HD66791_CTRL_ADDR = (_data & 0xFF); \
				LCD_delay_HD66791(); \
			}

			#define LCD_DataWrite_HD66791(_data) \
			{\
				*(volatile kal_uint8 *)LCD_HD66791_DATA_ADDR = ((_data & 0xFF00) >>8); \
				LCD_delay_HD66791(); \
				*(volatile kal_uint8 *)LCD_HD66791_DATA_ADDR = (_data & 0xFF); \
				LCD_delay_HD66791(); \
			}
			
	#endif /* LCD_CMD_DMA_MODE */
	
	#define LCD_RAMWrite_HD66791(_data)\
			{\
				*((volatile unsigned char *) LCD_HD66791_DATA_ADDR) = ((_data & 0xFF00) >>8);\
				LCD_delay_HD66791(); \
				*((volatile unsigned char *) LCD_HD66791_DATA_ADDR) = (_data & 0xFF);\
				LCD_delay_HD66791(); \
	    }
		
	

#endif  //#if (defined(MT6218B) || defined(MT6219)

#endif //#if (defined (__GD85_2_TCL_DRV_LCD_RENESAS_HD66791__))

/* END 2005-03-15 TCL-xjinming added for GD85-2 LCD_MAIN..... */







/*************************************************************/
/* HITACHI Main S6D0123,64k/262k Color, 128x160 Parallel(TFT)*/
/*************************************************************/

#if (defined (__GD85_1_TCL_DRV_LCD_S6D0123_HITACHI__))
#if ((defined(MT6208)) || (defined(MT6218)) ||(defined(MT6205B))||(defined(MT6218B))||(defined(MT6217))) //20050415 yguangyong added 6217

   #ifdef MCU_13M
      #define LCD_delay_S6D0123()
   #endif	/* MCU_13M */
   
   #ifdef MCU_26M
      #define LCD_delay_S6D0123()\
         {\
         	kal_uint16  _stat;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         }
   #endif	/* MCU_26M */
   
   #ifdef MCU_39M
      #define LCD_delay_S6D0123()\
         {\
         	kal_uint16  _stat;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         }
   #endif	/* MCU_39M */

   #ifdef MCU_52M
      #define LCD_delay_S6D0123()\
         {\
         	kal_uint16  _stat;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         	_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
         }
      #ifdef DUAL_LCD
			#define LCD_delay_ST7565() \
			{\
				kal_uint16  _stat;\
				_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
				_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
				_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
				_stat = *(volatile kal_uint16  *)LCD_DUMMYADDR;\
			}
      #endif   
   #endif	/* MCU_52M */

#endif	/* MT6208 */


#if (defined(MT6218B) || defined(MT6219)|| defined(MT6217)) //20050415 yguangyong added 6217
	#ifdef LCD_CMD_DMA_MODE
		#define LCD_SEND_DMA_CMD(n) \
			{\
			DISABLE_LCD_TRANSFER_COMPLETE_INT;\
			SET_LCD_ROI_CTRL_NUMBER_OF_CMD(n);\
			ENABLE_LCD_ROI_CTRL_CMD_FIRST;\
			SET_LCD_ROI_WINDOW_SIZE(0,0);\
			START_LCD_TRANSFER;\
			while (LCD_IS_RUNNING) {};\
			}

			#ifdef LCD16BitMode	/*mao add*/
			#define LCD_CtrlWrite_S6D0123(_data) \
			{\
				SET_LCD_CMD_PARAMETER(0,LCD_CMD,(_data));\
				LCD_SEND_DMA_CMD(1);\
			}
			#else/* LCD 8 bit mode */		
			#define LCD_CtrlWrite_S6D0123(_data) \
			{\
				SET_LCD_CMD_PARAMETER(0,LCD_CMD,(_data & 0xFF00 )>>8);\
				SET_LCD_CMD_PARAMETER(1,LCD_CMD,(_data & 0xFF));\
				LCD_SEND_DMA_CMD(2);\
			}
			#endif

			#ifdef LCD16BitMode	/*mao add*/
			#define LCD_DataWrite_S6D0123(_data) \
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💿 文件大小 28 K
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