bl_init.c

MTK 平台启动源码

/*****************************************************************************
*  Copyright Statement:
*  --------------------
*  This software is protected by Copyright and the information contained
*  herein is confidential. The software may not be copied and the information
*  contained herein may not be used or disclosed except with the written
*  permission of MediaTek Inc. (C) 2005
*
*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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*****************************************************************************/

/*****************************************************************************
 *
 * Filename:
 * ---------
 *   bl_Init.c
 *
 * Project:
 * --------
 *   Bootloader
 *
 * Description:
 * ------------
 *   This file defines the initialization functions of bootloader
 *
 * Author:
 * -------
 * -------
 *
 *============================================================================
 *             HISTORY
 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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 *============================================================================
 ****************************************************************************/

#include <bl_types.h>
#include <bl_MTK_BB_REG.h>
#include <bl_init.h>

extern void NFIReconfigure(void);
extern void custom_setEMI(void);
extern kal_uint32 SST_Get_Secinfo(kal_uint32 rom_base, kal_bool check_mac);
extern void SST_DTLB_Config (kal_uint32 secinfo_addr);


/**********************************************************
Description : Setting MCU PLL.
Input       : None
Output      : None
***********************************************************/
void INT_SetPLL(void)
{

#if ( defined(MT6228) || defined(MT6229) || defined(MT6230) )
{
   kal_uint16 i;

#ifdef EXT_26M
   // 1. Power on DSP_DIV2, MCU_DIV2, and CLKSQ
   *(volatile kal_uint16 *)0x80000320 = 0x9800;
   // 2. Enable MCU clock divider
   *(volatile kal_uint16 *)0x80000110 = 0x0008;
#elif defined (EXT_13M)
   // Power on CLKSQ
   *(volatile kal_uint16 *)0x80000320 = 0x0800;
#endif

   // 3. Boost MCU and DSP PLL (MDPLL) to 104MHz (MUST)
   *(volatile kal_uint16 *)0x80000100 = 0x0087;
   *(volatile kal_uint16 *)0x80000100 = 0x0007;

   // 4. Power ou MPLL
   *(volatile kal_uint16 *)0x80000320 = 0x4000;

   // 5. delay until PLL is stable, at least 50us
   for (i=0;i<0x100;i++);

   // 6. Define ARM(CPU, Data cache, TCM) and MCU PLL
#ifdef MCU_104M
   // MCU and BUS clock 2:1
   *(volatile kal_uint16 *)0x80000118 = 0x0703;
#elif defined MCU_52M
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000118 = 0x0303;
#elif defined MCU_26M
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000118 = 0x0101;
#elif defined MCU_13M
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000118 = 0x0000;
#endif

   // 7. Enable MPLL output
   *(volatile kal_uint16 *)0x80000110 |= 0x0002;
}
#endif /* ( defined(MT6228) || defined(MT6229) || defined(MT6230) ) */


#if defined(MT6225)
{
   kal_uint16 i;

#ifdef EXT_26M
   // 1. Power on DSP_DIV2, MCU_DIV2, and CLKSQ
   *(volatile kal_uint16 *)0x80000320 = 0x9800;
   // 2. Enable MCU clock divider
   *(volatile kal_uint16 *)0x80000110 = 0x0002;
#elif defined (EXT_13M)
   // Power on CLKSQ
   *(volatile kal_uint16 *)0x80000320 = 0x0800;
#endif

   // 3. Boost MCU and DSP PLL (MDPLL) to 104MHz (MUST)
   *(volatile kal_uint16 *)0x80000100 = 0x0080;
   *(volatile kal_uint16 *)0x80000100 = 0x0000;
   
   // 4. Power ou MPLL
   *(volatile kal_uint16 *)0x80000320 = 0x2000;
   
   // 5. delay until PLL is stable, at least 50us
   for (i=0;i<0x100;i++);
   
   // 6. Define ARM(CPU, Data cache, TCM) and MCU PLL
#ifdef MCU_104M   
   // MCU and BUS clock 2:1
   *(volatile kal_uint16 *)0x80000118 = 0x0703;
#elif defined MCU_52M
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000118 = 0x0303;
#elif defined MCU_26M
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000118 = 0x0101;
#elif defined MCU_13M
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000118 = 0x0000;   
#endif      

   // 7. Enable MPLL output
   *(volatile kal_uint16 *)0x80000100 |= 0x0010; 
}
#endif  /* MT6225 */

#if defined(MT6226) || defined(MT6227) || defined(MT6226M) || defined(MT6227D) || defined(MT6226D)
{
   kal_uint16 i;

#ifdef EXT_26M

   // 1. Power on DSP_DIV2, MPLL, DPLL, MCU_DIV2, and CLKSQ
   *(volatile kal_uint16 *)0x80000320 = ~0x04ff;
   // 2. Enable MCU clock divider
   *(volatile kal_uint16 *)0x80000108 = 0x0008;
   // 3. Reset the MPLL and setting MPLL to 52MHz
   *(volatile kal_uint16 *)0x80000100 = 0x0084;
   *(volatile kal_uint16 *)0x80000100 = 0x0004;
   // 4. delay until PLL is stable
   for (i=0;i<200;i++);
   // 5. Enable MPLL output
   *(volatile kal_uint16 *)0x80000108 = 0x000a;

#elif defined (EXT_13M) /* EXT_26M */

   // 1. Power on MPLL, DPLL and CLKSQ
   *(volatile kal_uint16 *)0x80000320 = ~0x94ff;
   // 3. Reset the MPLL and setting MPLL to 52MHz
   *(volatile kal_uint16 *)0x80000100 = 0x0084;
   *(volatile kal_uint16 *)0x80000100 = 0x0004;
   // 4. delay until PLL is stable
   for (i=0;i<200;i++);
   // 5. Enable MPLL output
   *(volatile kal_uint16 *)0x80000108 = 0x0002;
   
#endif   /* EXT_26M */

   // 6. Define ARM(CPU, Data cache) and MCU PLL
#ifdef MCU_52M
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000114 = 0x0003;
#elif defined (MCU_39M)
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000114 = 0x0002;
#elif defined (MCU_26M)
   // MCU and BUS clock 1:2
   *(volatile kal_uint16 *)0x80000114 = 0x0001;
#elif defined (MCU_13M)
   // MCU and BUS clock 1:4
   *(volatile kal_uint16 *)0x80000114 = 0x0000;
#endif
}
#endif   /* MT6226 || MT6227 || MT6226M || MT6227D || MT6226D */

}

/**********************************************************
Description : Setting MCU PLL.
Input       : None
Output      : None
***********************************************************/
void INT_RestorePLL(void)
{
#if ( defined(MT6228) || defined(MT6229) || defined(MT6230) )
{
   // 6. Define ARM(CPU, Data cache, TCM) and MCU PLL
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000118 = 0x0303;

   // 7. Disable MPLL output
   *(volatile kal_uint16 *)0x80000110 = 0x0000;
}
#endif /* MT6228 || MT6229 || MT6230 */

#if defined(MT6225)
{
   // 6. Define ARM(CPU, Data cache, TCM) and MCU PLL
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000118 = 0x0303;

   // 7. Enable MPLL output
   *(volatile kal_uint16 *)0x80000100 = 0x0000; 
}
#endif  /* MT6225 */

#if defined(MT6226) || defined(MT6227) || defined(MT6226M) || defined(MT6227D) || defined(MT6226D)
{
   // 6. Define ARM(CPU, Data cache) and MCU PLL
   // MCU and BUS clock 1:1
   *(volatile kal_uint16 *)0x80000114 = 0x0003;

   // 5. Disable MPLL output
//   *(volatile kal_uint16 *)0x80000108 = 0x0000;
}
#endif   /* MT6226 || MT6227 || MT6226M || MT6227D || MT6226D */
}

/**********************************************************
Description : Restart watchdog counter.
Input       : None
Output      : None
***********************************************************/

void WacthDogRestart(void)
{
   *(volatile kal_uint32 *)(WDT_RESTART) = WDT_RESTART_CMD;
}

/**********************************************************
Description : Disable watchdog counter.
Input       : None
Output      : None
***********************************************************/

void WacthDogDisable(void)
{
   *(volatile kal_uint32 *)(WDT_MODE) = WDT_DISABLE_CMD;
}

/**********************************************************
Description : Trigger Software Reset
Input       : None
Output      : None
***********************************************************/
void WatchDogResetAll(void)
{
   DRV_WriteReg(WDT_SWRST,WDT_SWRST_CMD);
   while(1);
}


/**********************************************************
Description : Wait for 32KHz clock srouce stable.
Input       : None
Output      : None
***********************************************************/
void WaitFor32KStable(void)
{
   kal_uint32 result;
   kal_uint16 result_low;
   kal_uint16 result_high;
   
   DRV_WriteReg(PDN_CLR2, PDN_CON2_TDMA);
   
   DRV_WriteReg(SM_FMDURATION,0);
       
   while(1)
   {
      DRV_Reg(SM_CTRL) |= SM_CTRL_FM_START;
      
      while(!(DRV_Reg(SM_STAT) & SM_STAT_FM_RDY));
      
      result_low = DRV_Reg(SM_FM_RESULT_LOW);
      result_high = DRV_Reg(SM_FM_RESULT_HIGH) & SM_FM_RESULT_HIGH_MASK;
      result = (result_low | (result_high << 16));
      
      if ((result < 950) && (result > 650))
         break;
   }
   
   DRV_WriteReg(PDN_SET2, PDN_CON2_TDMA);
}


/**********************************************************
Description : Start GPT Timer 3
Input       : None
Output      : None
***********************************************************/
void startGPTTImer3(void)
{

   DRV_WriteReg32(GPT_base + 0x001c, 0);
   DRV_WriteReg32(GPT_base + 0x0024, 0x07);
   DRV_WriteReg32(GPT_base + 0x001c, 1);

   return;
}


/**********************************************************
Description : Stop GPT Timer 3 and get the counter
Input       : None
Output      : 16bits counter duration
***********************************************************/
kal_uint16 stopGPTTImer3(void)
{
   kal_uint16 duration;
   
   duration = DRV_Reg32(GPT_base + 0x0020);
   DRV_WriteReg32(GPT_base + 0x001c, 0);
   
   return duration;
}


/**********************************************************
Description : Device initialization according to definition.
Input       : None
Output      : None
***********************************************************/
void DriverInit(void)
{
   kal_uint16  delay;

   for (delay=0; delay<0xffff; delay++);

   WacthDogRestart();
   
   WaitFor32KStable();
   
   WacthDogRestart();

   uart_init();

   NFIReconfigure();
   
   // Disable power-down control of DMA
   DRV_WriteReg32(PDN_CLR0, 0x01);
}




/**********************************************************
Description : initialization Procedure
Input       : None
Output      : None
***********************************************************/
void BootLoaderInit(void)
{
#if defined(_NAND_FLASH_BOOTING_) && defined(__USB_DOWNLOAD__) 
   /* USB_DOWNLOAD on NAND Flash */
   WacthDogDisable();
   INT_SetPLL();
   custom_setEMI();
#elif defined(__USB_DOWNLOAD__) 

#ifdef __SECURE_USB_DOWNLOAD__
   kal_uint32 secinfo_addr;

   secinfo_addr = SST_Get_Secinfo(0, KAL_FALSE);
   if (secinfo_addr != 0)
   {
      SST_DTLB_Config(secinfo_addr);
   }
#endif /* __SECURE_USB_DOWNLOAD__ */
   /* USB_DOWNLOAD on NOR Flash */
   WacthDogDisable();
   custom_setEMI();
   INT_SetPLL();
#elif defined(_NAND_FLASH_BOOTING_)
   /* NAND Flash Booting via UART */
   WacthDogRestart();
   INT_SetPLL();
   custom_setEMI();
#endif /* _NAND_FLASH_BOOTING_ && __USB_DOWNLOAD__ */

}