📄 指令摘要.txt
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CMPPD Compare packed double-precision floating-point values
CMPSD Compare scalar double-precision floating-point values
COMISD Perform ordered comparison of scalar double-precision floating-point values
and set flags in EFLAGS register
UCOMISD Perform unordered comparison of scalar double-precision floating-point values
and set flags in EFLAGS register.
5.6.1.5 SSE2 Shuffle and Unpack Instructions
SSE2 shuffle and unpack instructions shuffle or interleave double-precision floating-point
values in packed double-precision floating-point operands.
SHUFPD Shuffles values in packed double-precision floating-point operands
UNPCKHPD Unpacks and interleaves the high values from two packed double-preci-sion
floating-point operands
UNPCKLPD Unpacks and interleaves the low values from two packed double-precision
floating-point operands
5.6.1.6 SSE2 Conversion Instructions
SSE2 conversion instructions convert packed and individual doubleword integers into packed
and scalar double-precision floating-point values and vice versa. They also convert between
packed and scalar single-precision and double-precision floating-point values.
CVTPD2PI Convert packed double-precision floating-point values to packed double-word integers.
CVTTPD2PI Convert with truncation packed double-precision floating-point values to
packed doubleword integers
CVTPI2PD Convert packed doubleword integers to packed double-precision floating-point values
CVTPD2DQ Convert packed double-precision floating-point values to packed double-word integers
CVTTPD2DQ Convert with truncation packed double-precision floating-point values to
packed doubleword integers
CVTDQ2PD Convert packed doubleword integers to packed double-precision floating-point values
CVTPS2PD Convert packed single-precision floating-point values to packed double-precision
floating-point values
CVTPD2PS Convert packed double-precision floating-point values to packed single-precision
floating-point values
CVTSS2SD Convert scalar single-precision floating-point values to scalar double-precision
floating-point values
CVTSD2SS Convert scalar double-precision floating-point values to scalar single-precision
floating-point values
CVTSD2SI Convert scalar double-precision floating-point values to a doubleword integer
CVTTSD2SI Convert with truncation scalar double-precision floating-point values to
scalar doubleword integers
CVTSI2SD Convert doubleword integer to scalar double-precision floating-point value
5.6.2 SSE2 Packed Single-Precision Floating-Point Instructions
SSE2 packed single-precision floating-point instructions perform conversion operations on
single-precision floating-point and integer operands. These instructions represent enhancements
to the SSE single-precision floating-point instructions.
CVTDQ2PS Convert packed doubleword integers to packed single-precision floating-point values
CVTPS2DQ Convert packed single-precision floating-point values to packed double-word integers
CVTTPS2DQ Convert with truncation packed single-precision floating-point values to
packed doubleword integers
5.6.3 SSE2 128-Bit SIMD Integer Instructions
SSE2 SIMD integer instructions perform additional operations on packed words, doublewords,
and quadwords contained in XMM and MMX registers.
MOVDQA Move aligned double quadword.
MOVDQU Move unaligned double quadword
MOVQ2DQ Move quadword integer from MMX to XMM registers
MOVDQ2Q Move quadword integer from XMM to MMX registers
PMULUDQ Multiply packed unsigned doubleword integers
PADDQ Add packed quadword integers
PSUBQ Subtract packed quadword integers
PSHUFLW Shuffle packed low words
PSHUFHW Shuffle packed high words
PSHUFD Shuffle packed doublewords
PSLLDQ Shift double quadword left logical
PSRLDQ Shift double quadword right logical
PUNPCKHQDQ Unpack high quadwords
PUNPCKLQDQ Unpack low quadwords
5.6.4 SSE2 Cacheability Control and Ordering Instructions
SSE2 cacheability control instructions provide additional operations for caching of non-temporal
data when storing data from XMM registers to memory. LFENCE and MFENCE
provide additional control of instruction ordering on store operations.
CLFLUSH Flushes and invalidates a memory operand and its associated cache line
from all levels of the processor’s cache hierarchy
LFENCE Serializes load operations
MFENCE Serializes load and store operations
PAUSE Improves the performance of spin-wait loops
MASKMOVDQU Non-temporal store of selected bytes from an XMM register into memory
MOVNTPD Non-temporal store of two packed double-precision floating-point values
from an XMM register into memory
MOVNTDQ Non-temporal store of double quadword from an XMM register into memory
MOVNTI Non-temporal store of a doubleword from a general-purpose register into memory
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;SSE3指令
SSE3 PROC
SSE3 ENDP
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5.7 SSE3 INSTRUCTIONS
The SSE3 extensions offers 13 instructions that accelerate performance of Streaming SIMD
Extensions technology, Streaming SIMD Extensions 2 technology, and x87-FP math capabili-ties.
These instructions can be grouped into the following categories:
* One x87FPU instruction used in integer conversion
* One SIMD integer instruction that addresses unaligned data loads
* Two SIMD floating-point packed ADD/SUB instructions
* Four SIMD floating-point horizontal ADD/SUB instructions
* Three SIMD floating-point LOAD/MOVE/DUPLICATE instructions
* Two thread synchronization instructions
SSE3 instructions can only be executed on IA-32 processors that support SSE3 extensions.
Support for these instructions can be detected with the CPUID instruction. See the description
of the CPUID instruction in Chapter 3, Instruction Set Reference, A-M, of the IA-32 Intel(R)
Architecture Software Developer’s Manual, Volume 2A.
The sections that follow describe each subgroup.
5.7.1 SSE3 x87-FP Integer Conversion Instruction
FISTTP Behaves like the FISTP instruction but uses truncation, irrespective of the
rounding mode specified in the floating-point control word (FCW)
5.7.2 SSE3 Specialized 128-bit Unaligned Data Load Instruction
LDDQU Special 128-bit unaligned load designed to avoid cache line splits
5.7.3 SSE3 SIMD Floating-Point Packed ADD/SUB Instructions
ADDSUBPS Performs single-precision addition on the second and fourth pairs of 32-bit
data elements within the operands, single-precision subtraction on the first
and third pairs
ADDSUBPD Performs double-precision addition on the second pair of quadwords, and
double-precision subtraction on the first pair
5.7.4 SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions
HADDPS Performs a single-precision addition on contiguous data elements. The
first data element of the result is obtained by adding the first and second
elements of the first operand, the second element by adding the third and
fourth elements of the first operand, the third by adding the first and
second elements of the second operand, and the fourth by adding the third
and fourth elements of the second operand.
HSUBPS Performs a single-precision subtraction on contiguous data elements. The
first data element of the result is obtained by subtracting the second
element of the first operand from the first element of the first operand, the
second element by subtracting the fourth element of the first operand from
the third element of the first operand, the third by subtracting the second
element of the second operand from the first element of the second
operand, and the fourth by subtracting the fourth element of the second
operand from the third element of the second operand.
HADDPD Performs a double-precision addition on contiguous data elements. The
first data element of the result is obtained by adding the first and second
elements of the first operand, the second element by adding the first and
second elements of the second operand.
HSUBPD Performs a double-precision subtraction on contiguous data elements. The
first data element of the result is obtained by subtracting the second
element of the first operand from the first element of the first operand, the
second element by subtracting the second element of the second operand
from the first element of the second operand.
5.7.5 SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE nstructions
MOVSHDUP Loads/moves 128 bits, duplicating the second and fourth 32-bit data elements
MOVSLDUP Loads/moves 128 bits, duplicating the first and third 32-bit data elements
MOVDDUP Loads/moves 64 bits (bits[63:0] if the source is a register) and returns the
same 64 bits in both the lower and upper halves of the 128-bit resultregister
duplicates the 64 bits from the source
5.7.6 SSE3 Agent Synchronization Instructions
MONITOR Sets up an address range used to monitor write-back stores
MWAIT Enables a logical processor to enter into an optimized state while waiting
for a write-back store to the address range set up by the MONITOR instruction
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;系统指令
SYS PROC
SYS ENDP
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5.8 SYSTEM INSTRUCTIONS
The following system instructions are used to control those functions of the processor that are
provided to support for operating systems and executives.
LGDT Load global descriptor table (GDT) register
SGDT Store global descriptor table (GDT) register
LLDT Load local descriptor table (LDT) register
SLDT Store local descriptor table (LDT) register
LTR Load task register
STR Store task register
LIDT Load interrupt descriptor table (IDT) register
SIDT Store interrupt descriptor table (IDT) register
MOV Load and store control registers
LMSW Load machine status word
SMSW Store machine status word
CLTS Clear the task-switched flag
ARPL Adjust requested privilege level
LAR Load access rights
LSL Load segment limit
VERR Verify segment for reading
VERW Verify segment for writing
MOV Load and store debug registers
INVD Invalidate cache, no writeback
WBINVD Invalidate cache, with writeback
INVLPG Invalidate TLB Entry
LOCK (prefix) Lock Bus
HLT Halt processor
RSM Return from system management mode (SMM)
RDMSR Read model-specific register
WRMSR Write model-specific register
RDPMC Read performance monitoring counters
RDTSC Read time stamp counter
SYSENTER Fast System Call, transfers to a flat protected mode kernel at CPL = 0
SYSEXIT Fast System Call, transfers to a flat protected mode kernel at CPL = 3
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;64位指令
64 PROC
64 ENDP
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5.9 64-BIT MODE INSTRUCTIONS
The following instructions are introduced in 64-bit mode. This mode is a sub-mode of IA-32e mode.
CDQE Convert doubleword to quadword
CMPSQ Compare string operands
CMPXCHG16B Compare RDX:RAX with m128
LODSQ Load qword at address (R)SI into RAX
MOVSQ Move qword from address (R)SI to (R)DI
MOVZX (64-bits) Move doubleword to quadword, zero-extension
STOSQ Store RAX at address RDI
SWAPGS Exchanges current GS base register value with value in MSR address C0000102H
SYSCALL Fast call to privilege level 0 system procedures
SYSRET Return from fast system call
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;虚拟机指令？
VM PROC
VM ENDP
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5.10 VIRTUAL-MACHINE EXTENSIONS
The behavior of the VMCS-maintenance instructions is summarized below:
VMPTRLD Takes a single 64-bit source operand in memory. It makes the referenced
VMCS active and current.
VMPTRST Takes a single 64-bit destination operand that is in memory. Current-VMCS
pointer is stored into the destination operand.
VMCLEAR Takes a single 64-bit operand in memory. The instruction sets the launch
state of the VMCS referenced by the operand to clear, renders that
VMCS inactive, and ensures that data for the VMCS have been written to
the VMCS-data area in the referenced VMCS region.
VMREAD Reads a component from the VMCS (the encoding of that field is given in
a register operand) and stores it into a destination operand.
VMWRITE Writes a component to the VMCS (the encoding of that field is given in a
register operand) from a source operand.
The behavior of the VMX management instructions is summarized below:
VMCALL Allows a guest in VMX non-root operation to call the VMM for service.
A VM exit occurs, transferring control to the VMM.
VMLAUNCH Launches a virtual machine managed by the VMCS. A VM entry occurs,
transferring control to the VM.
VMRESUME Resumes a virtual machine managed by the VMCS. A VM entry occurs,
transferring control to the VM.
VMXOFF Causes the processor to leave VMX operation.
VMXON Takes a single 64-bit source operand in memory. It causes a logical
processor to enter VMX root operation and to use the memory referenced
by the operand to support VMX operation.⌨️ 快捷键说明
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