📄 指令摘要.txt
字号:
5.4.4 MMX Comparison Instructions
The compare instructions compare packed bytes, words, or doublewords.
PCMPEQB Compare packed bytes for equal
PCMPEQW Compare packed words for equal
PCMPEQD Compare packed doublewords for equal
PCMPGTB Compare packed signed byte integers for greater than
PCMPGTW Compare packed signed word integers for greater than
PCMPGTD Compare packed signed doubleword integers for greater than
5.4.5 MMX Logical Instructions
The logical instructions perform AND, AND NOT, OR, and XOR operations on quadword operands.
PAND Bitwise logical AND
PANDN Bitwise logical AND NOT
POR Bitwise logical OR
PXOR Bitwise logical exclusive OR
5.4.6 MMX Shift and Rotate Instructions
The shift and rotate instructions shift and rotate packed bytes, words, or doublewords, or quad-words
in 64-bit operands.
PSLLW Shift packed words left logical
PSLLD Shift packed doublewords left logical
PSLLQ Shift packed quadword left logical
PSRLW Shift packed words right logical
PSRLD Shift packed doublewords right logical
PSRLQ Shift packed quadword right logical
PSRAW Shift packed words right arithmetic
PSRAD Shift packed doublewords right arithmetic
5.4.7 MMX State Management Instructions
The EMMS instruction clears the MMX state from the MMX registers.
EMMS Empty MMX state
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
;SSE指令(Streaming SIMD Extensions) SIMD(single-instruction multiple-data)
SSE PROC
SSE ENDP
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
5.5 SSE INSTRUCTIONS
SSE instructions represent an extension of the SIMD execution model introduced with the
MMX technology. For more detail on these instructions, see Chapter 10, Programming with
Streaming SIMD Extensions (SSE).
SSE instructions can only be executed on IA-32 processors that support SSE extensions.
Support for these instructions can be detected with the CPUID instruction. See the description
of the CPUID instruction in Chapter 3, Instruction Set Reference, A-M, of the IA-32 Intel(R)
Architecture Software Developer’s Manual, Volume 2A.
SSE instructions are divided into four subgroups (note that the first subgroup has subordinate
subgroups of its own):
* SIMD single-precision floating-point instructions that operate on the XMM registers
* MXSCR state management instructions
* 64-bit SIMD integer instructions that operate on the MMX registers
* Cacheability control, prefetch, and instruction ordering instructions
The following sections provide an overview of these groups.
5.5.1 SSE SIMD Single-Precision Floating-Point Instructions
These instructions operate on packed and scalar single-precision floating-point values located
in XMM registers and/or memory. This subgroup is further divided into the following subordi-
nate subgroups: data transfer, packed arithmetic, comparison, logical, shuffle and unpack, and
conversion instructions.
5.5.1.1 SSE Data Transfer Instructions
SSE data transfer instructions move packed and scalar single-precision floating-point operands
between XMM registers and between XMM registers and memory.
MOVAPS Move four aligned packed single-precision floating-point values between
XMM registers or between and XMM register and memory
MOVUPS Move four unaligned packed single-precision floating-point values
between XMM registers or between and XMM register and memory
MOVHPS Move two packed single-precision floating-point values to an from the
high quadword of an XMM register and memory
MOVHLPS Move two packed single-precision floating-point values from the high
quadword of an XMM register to the low quadword of another XMM register
MOVLPS Move two packed single-precision floating-point values to an from the
low quadword of an XMM register and memory
MOVLHPS Move two packed single-precision floating-point values from the low
quadword of an XMM register to the high quadword of another XMM register
MOVMSKPS Extract sign mask from four packed single-precision floating-point values
MOVSS Move scalar single-precision floating-point value between XMM registers
or between an XMM register and memory
5.5.1.2 SSE Packed Arithmetic Instructions
SSE packed arithmetic instructions perform packed and scalar arithmetic operations on packed and
scalar single-precision floating-point operands.
ADDPS Add packed single-precision floating-point values
ADDSS Add scalar single-precision floating-point values
SUBPS Subtract packed single-precision floating-point values
SUBSS Subtract scalar single-precision floating-point values
MULPS Multiply packed single-precision floating-point values
MULSS Multiply scalar single-precision floating-point values
DIVPS Divide packed single-precision floating-point values
DIVSS Divide scalar single-precision floating-point values
RCPPS Compute reciprocals of packed single-precision floating-point values
RCPSS Compute reciprocal of scalar single-precision floating-point values
SQRTPS Compute square roots of packed single-precision floating-point values
SQRTSS Compute square root of scalar single-precision floating-point values
RSQRTPS Compute reciprocals of square roots of packed single-precision floating-point values
RSQRTSS Compute reciprocal of square root of scalar single-precision floating-point values
MAXPS Return maximum packed single-precision floating-point values
MAXSS Return maximum scalar single-precision floating-point values
MINPS Return minimum packed single-precision floating-point values
MINSS Return minimum scalar single-precision floating-point values
5.5.1.3 SSE Comparison Instructions
SSE compare instructions compare packed and scalar single-precision floating-point operands.
!CMPPS Compare packed single-precision floating-point values
!CMPSS Compare scalar single-precision floating-point values
COMISS Perform ordered comparison of scalar single-precision floating-point values
And set flags in EFLAGS register
UCOMISS Perform unordered comparison of scalar single-precision floating-point values
and set flags in EFLAGS register
5.5.1.4 SSE Logical Instructions
SSE logical instructions perform bitwise AND, AND NOT, OR, and XOR operations on packed
single-precision floating-point operands.
ANDPS Perform bitwise logical AND of packed single-precision floating-point values
ANDNPS Perform bitwise logical AND NOT of packed single-precision floating-point values
ORPS Perform bitwise logical OR of packed single-precision floating-point values
XORPS Perform bitwise logical XOR of packed single-precision floating-point values
5.5.1.5 SSE Shuffle and Unpack Instructions
SSE shuffle and unpack instructions shuffle or interleave single-precision floating-point values in
packed single-precision floating-point operands.
SHUFPS Shuffles values in packed single-precision floating-point operands
UNPCKHPS Unpacks and interleaves the two high-order values from two single-preci-sion
floating-point operands
UNPCKLPS Unpacks and interleaves the two low-order values from two single-preci-sion
floating-point operands
5.5.1.6 SSE Conversion Instructions
SSE conversion instructions convert packed and individual doubleword integers into packed
and scalar single-precision floating-point values and vice versa.
CVTPI2PS Convert packed doubleword integers to packed single-precision floating-point values
CVTSI2SS Convert doubleword integer to scalar single-precision floating-point value
CVTPS2PI Convert packed single-precision floating-point values to packed double-word integers
CVTTPS2PI Convert with truncation packed single-precision floating-point values to
packed doubleword integers
CVTSS2SI Convert a scalar single-precision floating-point value to a doubleword integer
CVTTSS2SI Convert with truncation a scalar single-precision floating-point value to a scalar
doubleword integer
5.5.2 SSE MXCSR State Management Instructions
MXCSR state management instructions allow saving and restoring the state of the MXCSR
control and status register.
LDMXCSR Load MXCSR register
STMXCSR Save MXCSR register state
5.5.3 SSE 64-Bit SIMD Integer Instructions
These SSE 64-bit SIMD integer instructions perform additional operations on packed bytes,
words, or doublewords contained in MMX registers. They represent enhancements to the
MMX instruction set described in Section 5.4, MMX(TM) Instructions.
PAVGB Compute average of packed unsigned byte integers
PAVGW Compute average of packed unsigned byte integers
PEXTRW Extract word
!PINSRW Insert word
PMAXUB Maximum of packed unsigned byte integers
PMAXSW Maximum of packed signed word integers
PMINUB Minimum of packed unsigned byte integers
PMINSW Minimum of packed signed word integers
PMOVMSKB Move byte mask
PMULHUW Multiply packed unsigned integers and store high result
PSADBW Compute sum of absolute differences
PSHUFW Shuffle packed integer word in MMX register
5.5.4 SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions
The cacheability control instructions provide control over the caching of non-temporal data
when storing data from the MMX and XMM registers to memory. The PREFETCHh allows data
to be prefetched to a selected cache level. The SFENCE instruction controls instruction ordering
on store operations.
MASKMOVQ Non-temporal store of selected bytes from an MMX register into memory
MOVNTQ Non-temporal store of quadword from an MMX register into memory
MOVNTPS Non-temporal store of four packed single-precision floating-point values
from an XMM register into memory
PREFETCHh Load 32 or more of bytes from memory to a selected level of the
processor’s cache hierarchy
SFENCE Serializes store operations
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
;SSE2指令
SSE2 PROC
SSE2 ENDP
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
5.6 SSE2 INSTRUCTIONS
SSE2 extensions represent an extension of the SIMD execution model introduced with MMX
technology and the SSE extensions. SSE2 instructions operate on packed double-precision
floating-point operands and on packed byte, word, doubleword, and quadword operands located
in the XMM registers. For more detail on these instructions, see Chapter 11, Programming with
Streaming SIMD Extensions 2 (SSE2).
SSE2 instructions can only be executed on IA-32 processors that support the SSE2 extensions.
Support for these instructions can be detected with the CPUID instruction. See the description
of the CPUID instruction in Chapter 3, Instruction Set Reference, A-M, of the IA-32 Intel(R)
Architecture Software Developer’s Manual, Volume 2A.
These instructions are divided into four subgroups (note that the first subgroup is further divided
into subordinate subgroups):
* Packed and scalar double-precision floating-point instructions
* Packed single-precision floating-point conversion instructions
* 128-bit SIMD integer instructions
* Cacheability-control and instruction ordering instructions
The following sections give an overview of each subgroup.
5.6.1 SSE2 Packed and Scalar Double-Precision Floating-Point Instructions
SSE2 packed and scalar double-precision floating-point instructions are divided into the
following subordinate subgroups: data movement, arithmetic, comparison, conversion, logical,
and shuffle operations on double-precision floating-point operands. These are introduced in the
sections that follow.
5.6.1.1 SSE2 Data Movement Instructions
SSE2 data movement instructions move double-precision floating-point data between XMM
registers and between XMM registers and memory.
MOVAPD Move two aligned packed double-precision floating-point values between
XMM registers or between and XMM register and memory
MOVUPD Move two unaligned packed double-precision floating-point values
between XMM registers or between and XMM register and memory
MOVHPD Move high packed double-precision floating-point value to an from the
high quadword of an XMM register and memory
MOVLPD Move low packed single-precision floating-point value to an from the low
quadword of an XMM register and memory
MOVMSKPD Extract sign mask from two packed double-precision floating-point values
MOVSD Move scalar double-precision floating-point value between XMM regis-ters
or between an XMM register and memory
5.6.1.2 SSE2 Packed Arithmetic Instructions
The arithmetic instructions perform addition, subtraction, multiply, divide, square root, and
maximum/minimum operations on packed and scalar double-precision floating-point operands.
ADDPD Add packed double-precision floating-point values
ADDSD Add scalar double precision floating-point values
SUBPD Subtract scalar double-precision floating-point values
SUBSD Subtract scalar double-precision floating-point values
MULPD Multiply packed double-precision floating-point values
MULSD Multiply scalar double-precision floating-point values
DIVPD Divide packed double-precision floating-point values
DIVSD Divide scalar double-precision floating-point values
SQRTPD Compute packed square roots of packed double-precision floating-point values
SQRTSD Compute scalar square root of scalar double-precision floating-point values
MAXPD Return maximum packed double-precision floating-point values
MAXSD Return maximum scalar double-precision floating-point values
MINPD Return minimum packed double-precision floating-point values
MINSD Return minimum scalar double-precision floating-point values
5.6.1.3 SSE2 Logical Instructions
SSE2 logical instructions preform AND, AND NOT, OR, and XOR operations on packed
double-precision floating-point values.
ANDPD Perform bitwise logical AND of packed double-precision floating-point values
ANDNPD Perform bitwise logical AND NOT of packed double-precision floating-point values
ORPD Perform bitwise logical OR of packed double-precision floating-point values
XORPD Perform bitwise logical XOR of packed double-precision floating-point values
5.6.1.4 SSE2 Compare Instructions
SSE2 compare instructions compare packed and scalar double-precision floating-point values
and return the results of the comparison either to the destination operand or to the EFLAGS register.
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -