📄 指令摘要.txt
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IN Read from a port
OUT Write to a port
INS/INSB Input string from port/Input byte string from port
INS/INSW Input string from port/Input word string from port
INS/INSD Input string from port/Input doubleword string from port
OUTS/OUTSB Output string to port/Output byte string to port
OUTS/OUTSW Output string to port/Output word string to port
OUTS/OUTSD Output string to port/Output doubleword string to port
5.1.10 Enter and Leave Instructions
These instructions provide machine-language support for procedure calls in block-structured languages.
ENTER High-level procedure entry
LEAVE High-level procedure exit
5.1.11 Flag Control (EFLAG) Instructions
The flag control instructions operate on the flags in the EFLAGS register.
STC Set carry flag
CLC Clear the carry flag
CMC Complement the carry flag
CLD Clear the direction flag
STD Set direction flag
LAHF Load flags into AH register
SAHF Store AH register into flags
PUSHF/PUSHFD Push EFLAGS onto stack
POPF/POPFD Pop EFLAGS from stack
STI Set interrupt flag
CLI Clear the interrupt flag
5.1.12 Segment Register Instructions
The segment register instructions allow far pointers (segment addresses) to be loaded into the segment registers.
LDS Load far pointer using DS
LES Load far pointer using ES
LFS Load far pointer using FS
LGS Load far pointer using GS
LSS Load far pointer using SS
5.1.13 Miscellaneous Instructions
The miscellaneous instructions provide such functions as loading an effective address,
executing a “no-operation,” and retrieving processor identification information.
LEA Load effective address
NOP No operation
UD2 Undefined instruction
XLAT/XLATB Table lookup translation
CPUID Processor Identification
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;浮点指令
X87_FPU PROC
X87_FPU ENDP
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5.2 X87 FPU INSTRUCTIONS
The x87 FPU instructions are executed by the processor’s x87 FPU. These instructions operate
on floating-point, integer, and binary-coded decimal (BCD) operands. For more detail on x87
FPU instructions, see Chapter 8, “Programming with the x87 FPU.”
These instructions are divided into the following subgroups: data transfer, load constants, and
FPU control instructions. The sections that follow introduce each subgroup.
5.2.1 x87 FPU Data Transfer Instructions
The data transfer instructions move floating-point, integer, and BCD values between
memory and the x87 FPU registers. They also perform conditional move operations on floating-point operands.
FLD Load floating-point value
FST Store floating-point value
FSTP Store floating-point value and pop
FILD Load integer
FIST Store integer
FISTP Store integer and pop
;注释：SSE3 provides an instruction FISTTP for integer conversion.
FBLD Load BCD
FBSTP Store BCD and pop
FXCH Exchange registers
FCMOVE Floating-point conditional move if equal
FCMOVNE Floating-point conditional move if not equal
FCMOVB Floating-point conditional move if below
FCMOVBE Floating-point conditional move if below or equal
FCMOVNB Floating-point conditional move if not below
FCMOVNBE Floating-point conditional move if not below or equal
FCMOVU Floating-point conditional move if unordered
FCMOVNU Floating-point conditional move if not unordered
5.2.2 x87 FPU Basic Arithmetic Instructions
The basic arithmetic instructions perform basic arithmetic operations on floating-point and integer operands.
FADD Add floating-point
FADDP Add floating-point and pop
FIADD Add integer
FSUB Subtract floating-point
FSUBP Subtract floating-point and pop
FISUB Subtract integer
FSUBR Subtract floating-point reverse
FSUBRP Subtract floating-point reverse and pop
FISUBR Subtract integer reverse
FMUL Multiply floating-point
FMULP Multiply floating-point and pop
FIMUL Multiply integer
FDIV Divide floating-point
FDIVP Divide floating-point and pop
FIDIV Divide integer
FDIVR Divide floating-point reverse
FDIVRP Divide floating-point reverse and pop
FIDIVR Divide integer reverse
FPREM Partial remainder
FPREM1 IEEE Partial remainder
FABS Absolute value
FCHS Change sign
FRNDINT Round to integer
FSCALE Scale by power of two
FSQRT Square root
FXTRACT Extract exponent and significand
5.2.3 x87 FPU Comparison Instructions
The compare instructions examine or compare floating-point or integer operands.
FCOM Compare floating-point
FCOMP Compare floating-point and pop
FCOMPP Compare floating-point and pop twice
FUCOM Unordered compare floating-point
FUCOMP Unordered compare floating-point and pop
FUCOMPP Unordered compare floating-point and pop twice
FICOM Compare integer
FICOMP Compare integer and pop
FCOMI Compare floating-point and set EFLAGS
FUCOMI Unordered compare floating-point and set EFLAGS
FCOMIP Compare floating-point, set EFLAGS, and pop
FUCOMIP Unordered compare floating-point, set EFLAGS, and pop
FTST Test floating-point (compare with 0.0)
FXAM Examine floating-point
5.2.4 x87 FPU Transcendental Instructions
The transcendental instructions perform basic trigonometric and logarithmic operations on floating-point operands.
FSIN Sine
FCOS Cosine
FSINCOS Sine and cosine
FPTAN Partial tangent
FPATAN Partial arctangent
F2XM1 2x - 1
FYL2X y*log2x
FYL2XP1 y*log2(x+1)
5.2.5 x87 FPU Load Constants Instructions
The load constants instructions load common constants, such as π, into the x87 floating-point registers.
FLD1 Load +1.0
FLDZ Load +0.0
FLDPI Load π
FLDL2E Load log2e
FLDLN2 Load loge2
FLDL2T Load log2 10
FLDLG2 Load log102
5.2.6 x87 FPU Control Instructions
The x87 FPU control instructions operate on the x87 FPU register stack and save and restore the x87 FPU state.
FINCSTP Increment FPU register stack pointer
FDECSTP Decrement FPU register stack pointer
FFREE Free floating-point register
FINIT Initialize FPU after checking error conditions
FNINIT Initialize FPU without checking error conditions
FCLEX Clear floating-point exception flags after checking for error conditions
FNCLEX Clear floating-point exception flags without checking for error conditions
FSTCW Store FPU control word after checking error conditions
FNSTCW Store FPU control word without checking error conditions
FLDCW Load FPU control word
FSTENV Store FPU environment after checking error conditions
FNSTENV Store FPU environment without checking error conditions
FLDENV Load FPU environment
FSAVE Save FPU state after checking error conditions
FNSAVE Save FPU state without checking error conditions
FRSTOR Restore FPU state
FSTSW Store FPU status word after checking error conditions
FNSTSW Store FPU status word without checking error conditions
WAIT/FWAIT Wait for FPU
FNOP FPU no operation
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
;浮点AND SIMD指令
FPU_SIMD PROC
FPU_SIMD ENDP
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5.3 X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS
Two state management instructions were introduced into the IA-32 architecture with the Pentium II processor family:
FXSAVE Save x87 FPU and SIMD state
FXRSTOR Restore x87 FPU and SIMD state
Initially, these instructions operated only on the x87 FPU (and MMX) registers to perform a fast
save and restore, respectively, of the x87 FPU and MMX state. With the introduction of SSE
extensions in the Pentium III processor family, these instructions were expanded to also save and
restore the state of the XMM and MXCSR registers.
See Section 10.5, “FXSAVE and FXRSTOR Instructions,” for more detail.
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
;MMX(MultiMedia eXtensions) 指令 (Vol. 1 5-14～16) single-instruction multiple-data(Vol. 1 2-12 )
MMX PROC
MMX ENDP
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
5.4 MMX(TM) INSTRUCTIONS
Four extensions have been introduced into the IA-32 architecture to permit IA-32 processors to
perform single-instruction multiple-data (SIMD) operations. These extensions include the
MMX technology, SSE extensions, SSE2 extensions, and SSE3 extensions. For a discussion that
puts SIMD instructions in their historical context, see Section 2.2.3, SIMD Instructions.
MMX instructions operate on packed byte, word, doubleword, or quadword integer operands
contained in memory, in MMX registers, and/or in general-purpose registers. For more detail on
these instructions, see Chapter 9, Programming with Intel(R) MMX(TM) Technology.
MMX instructions can only be executed on IA-32 processors that support the MMX technology.
Support for these instructions can be detected with the CPUID instruction. See the description
of the CPUID instruction in Chapter 3, Instruction Set Reference, A-M, of the IA-32 Intel(R)
Architecture Software Developer’s Manual, Volume 2A.
MMX instructions are divided into the following subgroups: data transfer, conversion, packed
arithmetic, comparison, logical, shift and rotate, and state management instructions. The
sections that follow introduce each subgroup.
;------------------------------------------------------
5.4.1 MMX Data Transfer Instructions
The data transfer instructions move doubleword and quadword operands between MMX regis-
ters and between MMX registers and memory.
MOVD Move doubleword
MOVQ Move quadword
5.4.2 MMX Conversion Instructions
The conversion instructions pack and unpack bytes, words, and doublewords
PACKSSWB Pack words into bytes with signed saturation
PACKSSDW Pack doublewords into words with signed saturation
PACKUSWB Pack words into bytes with unsigned saturation.
PUNPCKHBW Unpack high-order bytes
PUNPCKHWD Unpack high-order words
PUNPCKHDQ Unpack high-order doublewords
PUNPCKLBW Unpack low-order bytes
PUNPCKLWD Unpack low-order words
PUNPCKLDQ Unpack low-order doublewords
5.4.3 MMX Packed Arithmetic Instructions
The packed arithmetic instructions perform packed integer arithmetic on packed byte, word, and doubleword integers.
PADDB Add packed byte integers
PADDW Add packed word integers
PADDD Add packed doubleword integers
PADDSB Add packed signed byte integers with signed saturation
PADDSW Add packed signed word integers with signed saturation
PADDUSB Add packed unsigned byte integers with unsigned saturation
PADDUSW Add packed unsigned word integers with unsigned saturation
PSUBB Subtract packed byte integers
PSUBW Subtract packed word integers
PSUBD Subtract packed doubleword integers
PSUBSB Subtract packed signed byte integers with signed saturation
PSUBSW Subtract packed signed word integers with signed saturation
PSUBUSB Subtract packed unsigned byte integers with unsigned saturation
PSUBUSW Subtract packed unsigned word integers with unsigned saturation
PMULHW Multiply packed signed word integers and store high result
PMULLW Multiply packed signed word integers and store low result
PMADDWD Multiply and add packed word integers
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