📄 si4700.lss
字号:
71a: 8c b9 out 0x0c, r24 ; 12
//wdt_enable(WDTO_2S);
Si4700_Intialization();
71c: 3e dd rcall .-1412 ; 0x19a <Si4700_Intialization>
while(1){
//wdt_reset();
switch (com_buf) {
71e: 80 91 82 00 lds r24, 0x0082
722: 99 27 eor r25, r25
724: aa 27 eor r26, r26
726: bb 27 eor r27, r27
728: fc 01 movw r30, r24
72a: 31 97 sbiw r30, 0x01 ; 1
72c: ea 30 cpi r30, 0x0A ; 10
72e: f1 05 cpc r31, r1
730: b0 f7 brcc .-20 ; 0x71e <main+0x16>
732: ed 5e subi r30, 0xED ; 237
734: ff 4f sbci r31, 0xFF ; 255
736: 09 94 ijmp
case 1:
com_buf=0;
738: 10 92 82 00 sts 0x0082, r1
frq=Si4700_Channel_Seek_DOWN();
73c: af de rcall .-674 ; 0x49c <Si4700_Channel_Seek_DOWN>
frq/=100;
73e: 24 e6 ldi r18, 0x64 ; 100
740: 30 e0 ldi r19, 0x00 ; 0
742: 40 e0 ldi r20, 0x00 ; 0
744: 50 e0 ldi r21, 0x00 ; 0
746: f6 d0 rcall .+492 ; 0x934 <__udivmodsi4>
748: 79 01 movw r14, r18
74a: 8a 01 movw r16, r20
i=((frq/1000)<<12)|(((frq/100)%10)<<8)|(((frq/10)%10)<<4)|((frq/1)%10);
74c: ca 01 movw r24, r20
74e: b9 01 movw r22, r18
750: 28 ee ldi r18, 0xE8 ; 232
752: 33 e0 ldi r19, 0x03 ; 3
754: 40 e0 ldi r20, 0x00 ; 0
756: 50 e0 ldi r21, 0x00 ; 0
758: ed d0 rcall .+474 ; 0x934 <__udivmodsi4>
75a: 69 01 movw r12, r18
75c: dc 2c mov r13, r12
75e: cc 24 eor r12, r12
760: d2 94 swap r13
762: 40 ef ldi r20, 0xF0 ; 240
764: d4 22 and r13, r20
766: c8 01 movw r24, r16
768: b7 01 movw r22, r14
76a: 24 e6 ldi r18, 0x64 ; 100
76c: 30 e0 ldi r19, 0x00 ; 0
76e: 40 e0 ldi r20, 0x00 ; 0
770: 50 e0 ldi r21, 0x00 ; 0
772: e0 d0 rcall .+448 ; 0x934 <__udivmodsi4>
774: ca 01 movw r24, r20
776: b9 01 movw r22, r18
778: 2a e0 ldi r18, 0x0A ; 10
77a: 30 e0 ldi r19, 0x00 ; 0
77c: 40 e0 ldi r20, 0x00 ; 0
77e: 50 e0 ldi r21, 0x00 ; 0
780: d9 d0 rcall .+434 ; 0x934 <__udivmodsi4>
782: dc 01 movw r26, r24
784: cb 01 movw r24, r22
786: 98 2f mov r25, r24
788: 88 27 eor r24, r24
78a: c8 2a or r12, r24
78c: d9 2a or r13, r25
78e: c8 01 movw r24, r16
790: b7 01 movw r22, r14
792: 2a e0 ldi r18, 0x0A ; 10
794: 30 e0 ldi r19, 0x00 ; 0
796: 40 e0 ldi r20, 0x00 ; 0
798: 50 e0 ldi r21, 0x00 ; 0
79a: cc d0 rcall .+408 ; 0x934 <__udivmodsi4>
79c: ca 01 movw r24, r20
79e: b9 01 movw r22, r18
7a0: 2a e0 ldi r18, 0x0A ; 10
7a2: 30 e0 ldi r19, 0x00 ; 0
7a4: 40 e0 ldi r20, 0x00 ; 0
7a6: 50 e0 ldi r21, 0x00 ; 0
7a8: c5 d0 rcall .+394 ; 0x934 <__udivmodsi4>
7aa: dc 01 movw r26, r24
7ac: cb 01 movw r24, r22
7ae: 24 e0 ldi r18, 0x04 ; 4
7b0: 88 0f add r24, r24
7b2: 99 1f adc r25, r25
7b4: 2a 95 dec r18
7b6: e1 f7 brne .-8 ; 0x7b0 <main+0xa8>
7b8: c8 2a or r12, r24
7ba: d9 2a or r13, r25
7bc: c8 01 movw r24, r16
7be: b7 01 movw r22, r14
7c0: 2a e0 ldi r18, 0x0A ; 10
7c2: 30 e0 ldi r19, 0x00 ; 0
7c4: 40 e0 ldi r20, 0x00 ; 0
7c6: 50 e0 ldi r21, 0x00 ; 0
7c8: b5 d0 rcall .+362 ; 0x934 <__udivmodsi4>
7ca: dc 01 movw r26, r24
7cc: cb 01 movw r24, r22
7ce: c8 2a or r12, r24
7d0: d9 2a or r13, r25
while(!(UCSRA & (1<<UDRE)));UDR=i>>8;
7d2: 5d 9b sbis 0x0b, 5 ; 11
7d4: fe cf rjmp .-4 ; 0x7d2 <main+0xca>
7d6: 8d 2d mov r24, r13
7d8: 99 27 eor r25, r25
7da: 8c b9 out 0x0c, r24 ; 12
while(!(UCSRA & (1<<UDRE)));UDR=i;
7dc: 5d 9b sbis 0x0b, 5 ; 11
7de: fe cf rjmp .-4 ; 0x7dc <main+0xd4>
7e0: 54 c0 rjmp .+168 ; 0x88a <main+0x182>
break;
case 2:
com_buf=0;
7e2: 10 92 82 00 sts 0x0082, r1
frq=Si4700_Channel_Seek_UP();
7e6: c2 dd rcall .-1148 ; 0x36c <Si4700_Channel_Seek_UP>
frq/=100;
7e8: 24 e6 ldi r18, 0x64 ; 100
7ea: 30 e0 ldi r19, 0x00 ; 0
7ec: 40 e0 ldi r20, 0x00 ; 0
7ee: 50 e0 ldi r21, 0x00 ; 0
7f0: a1 d0 rcall .+322 ; 0x934 <__udivmodsi4>
7f2: 79 01 movw r14, r18
7f4: 8a 01 movw r16, r20
i=((frq/1000)<<12)|(((frq/100)%10)<<8)|(((frq/10)%10)<<4)|((frq/1)%10);
7f6: ca 01 movw r24, r20
7f8: b9 01 movw r22, r18
7fa: 28 ee ldi r18, 0xE8 ; 232
7fc: 33 e0 ldi r19, 0x03 ; 3
7fe: 40 e0 ldi r20, 0x00 ; 0
800: 50 e0 ldi r21, 0x00 ; 0
802: 98 d0 rcall .+304 ; 0x934 <__udivmodsi4>
804: 69 01 movw r12, r18
806: dc 2c mov r13, r12
808: cc 24 eor r12, r12
80a: d2 94 swap r13
80c: b0 ef ldi r27, 0xF0 ; 240
80e: db 22 and r13, r27
810: c8 01 movw r24, r16
812: b7 01 movw r22, r14
814: 24 e6 ldi r18, 0x64 ; 100
816: 30 e0 ldi r19, 0x00 ; 0
818: 40 e0 ldi r20, 0x00 ; 0
81a: 50 e0 ldi r21, 0x00 ; 0
81c: 8b d0 rcall .+278 ; 0x934 <__udivmodsi4>
81e: ca 01 movw r24, r20
820: b9 01 movw r22, r18
822: 2a e0 ldi r18, 0x0A ; 10
824: 30 e0 ldi r19, 0x00 ; 0
826: 40 e0 ldi r20, 0x00 ; 0
828: 50 e0 ldi r21, 0x00 ; 0
82a: 84 d0 rcall .+264 ; 0x934 <__udivmodsi4>
82c: dc 01 movw r26, r24
82e: cb 01 movw r24, r22
830: 98 2f mov r25, r24
832: 88 27 eor r24, r24
834: c8 2a or r12, r24
836: d9 2a or r13, r25
838: c8 01 movw r24, r16
83a: b7 01 movw r22, r14
83c: 2a e0 ldi r18, 0x0A ; 10
83e: 30 e0 ldi r19, 0x00 ; 0
840: 40 e0 ldi r20, 0x00 ; 0
842: 50 e0 ldi r21, 0x00 ; 0
844: 77 d0 rcall .+238 ; 0x934 <__udivmodsi4>
846: ca 01 movw r24, r20
848: b9 01 movw r22, r18
84a: 2a e0 ldi r18, 0x0A ; 10
84c: 30 e0 ldi r19, 0x00 ; 0
84e: 40 e0 ldi r20, 0x00 ; 0
850: 50 e0 ldi r21, 0x00 ; 0
852: 70 d0 rcall .+224 ; 0x934 <__udivmodsi4>
854: dc 01 movw r26, r24
856: cb 01 movw r24, r22
858: f4 e0 ldi r31, 0x04 ; 4
85a: 88 0f add r24, r24
85c: 99 1f adc r25, r25
85e: fa 95 dec r31
860: e1 f7 brne .-8 ; 0x85a <main+0x152>
862: c8 2a or r12, r24
864: d9 2a or r13, r25
866: c8 01 movw r24, r16
868: b7 01 movw r22, r14
86a: 2a e0 ldi r18, 0x0A ; 10
86c: 30 e0 ldi r19, 0x00 ; 0
86e: 40 e0 ldi r20, 0x00 ; 0
870: 50 e0 ldi r21, 0x00 ; 0
872: 60 d0 rcall .+192 ; 0x934 <__udivmodsi4>
874: dc 01 movw r26, r24
876: cb 01 movw r24, r22
878: c8 2a or r12, r24
87a: d9 2a or r13, r25
while(!(UCSRA & (1<<UDRE)));UDR=i>>8;
87c: 5d 9b sbis 0x0b, 5 ; 11
87e: fe cf rjmp .-4 ; 0x87c <main+0x174>
880: 8d 2d mov r24, r13
882: 99 27 eor r25, r25
884: 8c b9 out 0x0c, r24 ; 12
while(!(UCSRA & (1<<UDRE)));UDR=i;
886: 5d 9b sbis 0x0b, 5 ; 11
888: fe cf rjmp .-4 ; 0x886 <main+0x17e>
88a: cc b8 out 0x0c, r12 ; 12
break;
88c: 48 cf rjmp .-368 ; 0x71e <main+0x16>
case 3:
com_buf=0;
88e: 10 92 82 00 sts 0x0082, r1
Si4700_mute_en();
892: 88 de rcall .-752 ; 0x5a4 <Si4700_mute_en>
break;
894: 44 cf rjmp .-376 ; 0x71e <main+0x16>
case 4:
com_buf=0;
896: 10 92 82 00 sts 0x0082, r1
Si4700_mute_dis();
89a: 9e de rcall .-708 ; 0x5d8 <Si4700_mute_dis>
break;
89c: 40 cf rjmp .-384 ; 0x71e <main+0x16>
case 5:
com_buf=0;
89e: 10 92 82 00 sts 0x0082, r1
Si4700_vol_up();
8a2: b5 de rcall .-662 ; 0x60e <Si4700_vol_up>
break;
8a4: 3c cf rjmp .-392 ; 0x71e <main+0x16>
case 6:
com_buf=0;
8a6: 10 92 82 00 sts 0x0082, r1
Si4700_vol_down();
8aa: e0 de rcall .-576 ; 0x66c <Si4700_vol_down>
break;
8ac: 38 cf rjmp .-400 ; 0x71e <main+0x16>
case 7:
com_buf=0;
8ae: 10 92 82 00 sts 0x0082, r1
Si4700_Channel_Selection(104000);
8b2: 60 e4 ldi r22, 0x40 ; 64
8b4: 76 e9 ldi r23, 0x96 ; 150
8b6: 81 e0 ldi r24, 0x01 ; 1
8b8: 90 e0 ldi r25, 0x00 ; 0
8ba: ca dc rcall .-1644 ; 0x250 <Si4700_Channel_Selection>
break;
8bc: 30 cf rjmp .-416 ; 0x71e <main+0x16>
case 8:
com_buf=0;
8be: 10 92 82 00 sts 0x0082, r1
OperationSi4700_2w(READ,reg, 2);
8c2: 42 e0 ldi r20, 0x02 ; 2
8c4: be 01 movw r22, r28
8c6: 6f 5f subi r22, 0xFF ; 255
8c8: 7f 4f sbci r23, 0xFF ; 255
8ca: 81 e2 ldi r24, 0x21 ; 33
8cc: da db rcall .-2124 ; 0x82 <OperationSi4700_2w>
while(!(UCSRA & (1<<UDRE)));UDR=reg[1];
8ce: 5d 9b sbis 0x0b, 5 ; 11
8d0: fe cf rjmp .-4 ; 0x8ce <main+0x1c6>
8d2: 8a 81 ldd r24, Y+2 ; 0x02
8d4: 8c b9 out 0x0c, r24 ; 12
break;
8d6: 23 cf rjmp .-442 ; 0x71e <main+0x16>
case 9:
com_buf=0;
8d8: 10 92 82 00 sts 0x0082, r1
reg[0]=0x60;
8dc: 80 e6 ldi r24, 0x60 ; 96
8de: 03 c0 rjmp .+6 ; 0x8e6 <main+0x1de>
OperationSi4700_2w(WRITE,reg, 1);//mono
break;
case 10:
com_buf=0;
8e0: 10 92 82 00 sts 0x0082, r1
reg[0]=0x40;
8e4: 80 e4 ldi r24, 0x40 ; 64
8e6: 89 83 std Y+1, r24 ; 0x01
OperationSi4700_2w(WRITE,reg, 1);//strero
8e8: 41 e0 ldi r20, 0x01 ; 1
8ea: be 01 movw r22, r28
8ec: 6f 5f subi r22, 0xFF ; 255
8ee: 7f 4f sbci r23, 0xFF ; 255
8f0: 80 e2 ldi r24, 0x20 ; 32
8f2: c7 db rcall .-2162 ; 0x82 <OperationSi4700_2w>
break;
8f4: 14 cf rjmp .-472 ; 0x71e <main+0x16>
000008f6 <__mulsi3>:
8f6: 62 9f mul r22, r18
8f8: d0 01 movw r26, r0
8fa: 73 9f mul r23, r19
8fc: f0 01 movw r30, r0
8fe: 82 9f mul r24, r18
900: e0 0d add r30, r0
902: f1 1d adc r31, r1
904: 64 9f mul r22, r20
906: e0 0d add r30, r0
908: f1 1d adc r31, r1
90a: 92 9f mul r25, r18
90c: f0 0d add r31, r0
90e: 83 9f mul r24, r19
910: f0 0d add r31, r0
912: 74 9f mul r23, r20
914: f0 0d add r31, r0
916: 65 9f mul r22, r21
918: f0 0d add r31, r0
91a: 99 27 eor r25, r25
91c: 72 9f mul r23, r18
91e: b0 0d add r27, r0
920: e1 1d adc r30, r1
922: f9 1f adc r31, r25
924: 63 9f mul r22, r19
926: b0 0d add r27, r0
928: e1 1d adc r30, r1
92a: f9 1f adc r31, r25
92c: bd 01 movw r22, r26
92e: cf 01 movw r24, r30
930: 11 24 eor r1, r1
932: 08 95 ret
00000934 <__udivmodsi4>:
934: a1 e2 ldi r26, 0x21 ; 33
936: 1a 2e mov r1, r26
938: aa 1b sub r26, r26
93a: bb 1b sub r27, r27
93c: fd 01 movw r30, r26
93e: 0d c0 rjmp .+26 ; 0x95a <__udivmodsi4_ep>
00000940 <__udivmodsi4_loop>:
940: aa 1f adc r26, r26
942: bb 1f adc r27, r27
944: ee 1f adc r30, r30
946: ff 1f adc r31, r31
948: a2 17 cp r26, r18
94a: b3 07 cpc r27, r19
94c: e4 07 cpc r30, r20
94e: f5 07 cpc r31, r21
950: 20 f0 brcs .+8 ; 0x95a <__udivmodsi4_ep>
952: a2 1b sub r26, r18
954: b3 0b sbc r27, r19
956: e4 0b sbc r30, r20
958: f5 0b sbc r31, r21
0000095a <__udivmodsi4_ep>:
95a: 66 1f adc r22, r22
95c: 77 1f adc r23, r23
95e: 88 1f adc r24, r24
960: 99 1f adc r25, r25
962: 1a 94 dec r1
964: 69 f7 brne .-38 ; 0x940 <__udivmodsi4_loop>
966: 60 95 com r22
968: 70 95 com r23
96a: 80 95 com r24
96c: 90 95 com r25
96e: 9b 01 movw r18, r22
970: ac 01 movw r20, r24
972: bd 01 movw r22, r26
974: cf 01 movw r24, r30
976: 08 95 ret
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