📄 rda5800.c
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#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include <avr/wdt.h>
#include <avr/eeprom.h>
#define DEBUG 0
#define F_CPU 8000000UL
#define BIT_SET(a,b) a|=(1<<b)
#define BIT_CLR(a,b) a&=(~(1<<b))
#define BIT_INV(a,b) a^=(1<<b)
#define BIT_STATUS(a,b) ((a&(1<<b))>>b)
uint8_t g_count0;
#define HEAD_T 12800
#define HIGH_T 2100
#define LOW_T 1000
#define en_t1_us_int(i) {TCNT1=65536-i;BIT_SET(TIMSK,2);}
#define dis_t1_int() {BIT_CLR(TIMSK,2);}
#define en_t0_64us_int() {TCNT0=g_count0;en_HW_tout=1;BIT_SET(TIMSK,TOIE0);}
#define dis_t0_int() {BIT_CLR(TIMSK,TOIE0);en_HW_tout=0;}
#ifdef HW_useICP1
#define HW_PIN BIT_STATUS(PIND,6)
#define SET_ICP1_UP_TRIG BIT_SET(TCCR1B,6)
#define SET_ICP1_FALL_TRIG BIT_CLR(TCCR1B,6)
#define en_icp1_int() {BIT_SET(TIMSK,1);}
#define dis_icp1_int() {BIT_CLR(TIMSK,1);}
#define CLR_ICF1 BIT_SET(TIFR,5)
#else
#define HW_PIN BIT_STATUS(PIND,3)
#define SET_INT1_UP_TRIG MCUCR|=(1<<ISC11)|(1<<ISC10);
#define SET_INT1_FALL_TRIG MCUCR|=(1<<ISC11);
#define en_int1_int() GICR|=(1<<INT1);
#define dis_int1_int() GICR&=(~(1<<INT1));
#endif
#define HEAD_NEG_T 9000
#define beep() {BIT_CLR(PORTA,6);_delay_ms(10);BIT_SET(PORTA,6);}
#define KEY_PRESS !BIT_STATUS(PINC,4)
/**************communicate***********************/
#define RB8 BIT_STATUS(UCSRB,1)
#define TB8(i) {if(i) BIT_SET(UCSRB,0);else BIT_CLR(UCSRB,0);}
#define MMCS BIT_STATUS(UCSRA,0)
#define MMC(i) {if(i) BIT_SET(UCSRA,0);else BIT_CLR(UCSRA,0);}
#define SLA_ADR 1
#define HOST_ADR 0
#define BCT 0xff
#define HOST_START 1
#define HOST_MOD 2
#define HOST_CODE 3
#define HOST_ASK_RESULT 4
#define EEP_ADR_CODE 0
#define CMD_NORMAL_RESULT 1
#define CMD_STUDY_RESULT 2
#define LED_Y(i) {if(i==0) BIT_SET(PORTB,7);else if(i==1) BIT_CLR(PORTB,7);else BIT_INV(PORTB,7);}
#define LED_G(i) {if(i==0) BIT_SET(PORTD,7);else if(i==1) BIT_CLR(PORTD,7);else BIT_INV(PORTD,7);}
static volatile uint8_t EventNum=0,flag_HWdata=0,en_HW_tout=0,step,en_rx_tout,len,cmd,flag_com_data,g_flag_speed,
com_rx_buf[100],HW_data,HW_num,err_buf[50],err_num,g_direction,en_led_flash;
static volatile uint32_t buffer;
static volatile enum{
HEAD_DET,
DATA_DET
}hw_det;
static volatile enum{
NORMAL=0,
STUDY
}mod;
void ini_uart(uint16_t m_baud)
{
uint16_t ubrr;
/* 设置波特率*/
ubrr=F_CPU/8/m_baud-1;
UBRRH = (uint8_t)(ubrr>>8);
UBRRL = (uint8_t)ubrr;
UCSRA = (1<<U2X);
//MMC(1);//多机通信使能
/* 设置帧格式: 9 个数据位, 1 个停止位*/
UCSRC = (1<<URSEL)|(1<<UCSZ0)|(1<<UCSZ1)|(1<<UCSZ2);
/* 接收器与发送器终端使能,接收器与发送器使能*/
UCSRB = (1<<RXCIE)/*|(1<<TXCIE)*/|(1<<RXEN)|(1<<TXEN);
}
void ini_tc0(void){
//TCNT0 = 158;
//TIFR|=(1<<TOV0);
//TIMSK|=(1<<TOIE0);
//TCCR0=_BV(CS02)|_BV(CS00); // 预分频 ck/1024
//TCCR0=_BV(CS01);// 预分频 ck/8
TCCR0=_BV(CS02);// 预分频 ck/256
}
void ini_port(void){
/*DDRB|=_BV(PB5)|_BV(PB1)|_BV(PB2)|_BV(PB3);
DDRB&=(~_BV(PB0))&(~_BV(PB4));
PORTB|=0xfF;
PORTC|=0xff;
DDRC|=_BV(PC5)|_BV(PC1)|_BV(PC2)|_BV(PC3)|_BV(PC4);
DDRC&=(~_BV(PC0));
PORTD|=0xff;
DDRD|=_BV(PD7)|_BV(PD6)|_BV(PD4);
DDRD&=(~_BV(PD2))&(~_BV(PD3))&(~_BV(PD5));*/
PORTD|=0xff;
DDRD|=_BV(PD5);
DDRD|=_BV(PD6);
PORTB|=0xff;
DDRB|=_BV(PB7);
//DDRD&=(~_BV(PD6));
//PORTA|=0xff;
//DDRA|=_BV(PA6);
}
uint8_t g_com_rx_data;
SIGNAL (SIG_UART_RECV) {
uint8_t f_100Hz;
g_com_rx_data=UDR;
while(!(UCSRA & (1<<UDRE)));//等待发送缓冲器为空
UDR=g_com_rx_data;
if(g_flag_speed){
f_100Hz=g_com_rx_data;
g_count0=10000/f_100Hz/64;
while(!(UCSRA & (1<<UDRE)));//等待发送缓冲器为空
UDR=g_count0;
}
}
void plus2pin(void){
if(g_direction)BIT_INV(PORTD,6);
else BIT_INV(PORTD,5);
}
//10ms中断1次
SIGNAL(SIG_OVERFLOW0)
{
static uint8_t time0,time1;
TCNT0=256-g_count0;
TIFR|=(1<<TOV0);
plus2pin();
}
void trans2host(uint8_t adr_t,uint8_t cmd_t,
uint8_t *sp_t,uint8_t num_t){
uint8_t i;
TB8(1);
while(!(UCSRA & (1<<UDRE)));//等待发送缓冲器为空
UDR=HOST_ADR;
TB8(0);
while(!(UCSRA & (1<<UDRE)));//等待发送缓冲器为空
UDR=num_t+2;
while(!(UCSRA & (1<<UDRE)));//等待发送缓冲器为空
UDR=adr_t;
while(!(UCSRA & (1<<UDRE)));//等待发送缓冲器为空
UDR=cmd_t;
for(i=0;i<num_t;i++){
while(!(UCSRA & (1<<UDRE)));//等待发送缓冲器为空
UDR=*(sp_t+i);
}
//LED_G(3);
}
int main(){
uint8_t *ptr;
ini_port();
ini_uart(9600);//9600
ini_tc0();
UDR=0xaa;
sei();
while(1){
switch (g_com_rx_data){
case 1://start
en_t0_64us_int();
g_com_rx_data=0;
g_flag_speed=0;
break;
case 2://stop
g_flag_speed=0;
g_com_rx_data=0;
dis_t0_int();
break;
case 3://deasil
g_flag_speed=0;
g_com_rx_data=0;
g_direction=0;
break;
case 4://anticlockwise
g_flag_speed=0;
g_com_rx_data=0;
g_direction=1;
break;
case 255://set speed
g_com_rx_data=0;
g_flag_speed=1;
break;
default: break;
}
}
}
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