create.cip

定制简单LED的IP核的设计源代码

CipWiz::SetVersion "14.2";
CipWiz::SetFlow "CREATE";
CipWiz::SetParameter "ProjectDir" "D:\_prj\Xilinx\Blog\Lab4";
CipWiz::SetParameter "IpName" "my_axi_ip";
CipWiz::SetParameter "IpVersion" "1.00.a";
CipWiz::SetParameter "SimulatorName" "isim";
CipWiz::SetParameter "HdlLanguage" "2";
CipWiz::SetParameter "BusType" "256";
CipWiz::SetParameter "IncludeIseFile" "TRUE";
CipWiz::SetParameter "IncludeXpsFile" "TRUE";
CipWiz::SetParameter "IncludeSoftwareDriverFile" "TRUE";
CipWiz::SetParameter "IncludeBFMSimulationFile" "FALSE";
CipWiz::SetParameter "IncludeSlaveAttachmentSupport" "TRUE";
CipWiz::SetParameter "IncludeMasterAttachmentSupport" "FALSE";
CipWiz::SetParameter "IncludeMirResetRegister" "FALSE";
CipWiz::SetParameter "IncludeFifoSupport" "FALSE";
CipWiz::SetParameter "IncludeInterruptSupport" "FALSE";
CipWiz::SetParameter "IncludeDMASupport" "FALSE";
CipWiz::SetParameter "IncludeBurstSupport" "FALSE";
CipWiz::SetParameter "IncludeUserRegisterSupport" "TRUE";
CipWiz::SetParameter "IncludeUserMasterSupport" "FALSE";
CipWiz::SetParameter "IncludeUserMemorySupport" "FALSE";
CipWiz::SetParameter "UseSlaveBurst" "FALSE";
CipWiz::SetParameter "UseMasterBurst" "FALSE";
CipWiz::SetParameter "UseReadFifo" "FALSE";
CipWiz::SetParameter "UseWriteFifo" "FALSE";
CipWiz::SetParameter "UseReadFifoPacketMode" "FALSE";
CipWiz::SetParameter "UseWriteFifoPacketMode" "FALSE";
CipWiz::SetParameter "UseReadFifoVacancyCalculation" "FALSE";
CipWiz::SetParameter "UseWriteFifoVacancyCalculation" "FALSE";
CipWiz::SetParameter "WriteFifoDataWidth" "0";
CipWiz::SetParameter "WriteFifoDepth" "0";
CipWiz::SetParameter "ReadFifoDataWidth" "0";
CipWiz::SetParameter "ReadFifoDepth" "0";
CipWiz::SetParameter "UseDeviceISC" "FALSE";
CipWiz::SetParameter "UseDevicePriorityEncoder" "FALSE";
CipWiz::SetParameter "NumberOfInterrupt" "0";
CipWiz::SetParameter "TypeOfInterrupt" "0";
CipWiz::SetParameter "TypeOfDMA" "0";
CipWiz::SetParameter "UseFastTransferProtocol" "FALSE";
CipWiz::SetParameter "BurstMaxSize" "0";
CipWiz::SetParameter "BurstPageSize" "0";
CipWiz::SetParameter "IncludeDPhaseTimer" "TRUE";
CipWiz::SetParameter "SlaveSideNativeDataWidth" "32";
CipWiz::SetParameter "SlaveBurstWriteBufferDepth" "0";
CipWiz::SetParameter "MasterSideNativeDataWidth" "0";
CipWiz::SetParameter "AXIMasterMaxBurstSize" "0";
CipWiz::SetParameter "AXIMasterWidthOfPort" "0";
CipWiz::SetParameter "AXIMasterAddrPipelineDepth" "0";
CipWiz::SetParameter "NumberOfUserRegister" "1";
CipWiz::SetParameter "UserRegisterDataWidth" "32";
CipWiz::SetParameter "WriteMode" "0";
CipWiz::SetParameter "HasInputFSL" "0";
CipWiz::SetParameter "HasOutputFSL" "0";
CipWiz::SetParameter "TotalInputData" "0";
CipWiz::SetParameter "TotalOutputData" "0";
CipWiz::SetParameter "NumOfInputArgs" "0";
CipWiz::SetParameter "NumOfOutputArgs" "0";
CipWiz::SetParameter "NumberOfUserMemoryBank" "0";
CipWiz::SetParameter "UserMemoryBankDataWidth" "0";
CipWiz::SetParameter "IpicSelectedPortNames" "Bus2IP_Clk|Bus2IP_Resetn|Bus2IP_Data|Bus2IP_BE|Bus2IP_RdCE|Bus2IP_WrCE|IP2Bus_Data|IP2Bus_RdAck|IP2Bus_WrAck|IP2Bus_Error|";
CipWiz::SetParameter "UserLogicModuleName" "0";
CipWiz::SetParameter "TypeOfUserLogicSource" "user_logic";