system_my_axi_ip_0_wrapper_xst.srp

来自「定制简单LED的IP核的设计源代码」· SRP 代码 · 共 887 行 · 第 1/4 页

 sm_write | 10
 sm_resp  | 11
----------------------

Optimizing unit <system_my_axi_ip_0_wrapper> ...

Optimizing unit <slave_attachment> ...

Optimizing unit <user_logic> ...
WARNING:Xst:1293 - FF/Latch <my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_1> has a constant value of 0 in block <system_my_axi_ip_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_1> has a constant value of 0 in block <system_my_axi_ip_0_wrapper>. This FF/Latch will be trimmed during the optimization process.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block system_my_axi_ip_0_wrapper, actual ratio is 0.
FlipFlop my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg has been replicated 1 time(s)
FlipFlop my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/ce_out_i_0 has been replicated 1 time(s)
FlipFlop my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1 has been replicated 1 time(s)
FlipFlop my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd2 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 79
 Flip-Flops                                            : 79

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : system_my_axi_ip_0_wrapper.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 86
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 2
#      LUT3                        : 4
#      LUT4                        : 34
#      LUT5                        : 38
#      LUT6                        : 4
#      MUXF7                       : 2
# FlipFlops/Latches                : 79
#      FD                          : 9
#      FDR                         : 38
#      FDRE                        : 32

Device utilization summary:
---------------------------

Selected Device : 7z020clg484-1 


Slice Logic Utilization: 
 Number of Slice Registers:              79  out of  106400     0%  
 Number of Slice LUTs:                   83  out of  53200     0%  
    Number used as Logic:                83  out of  53200     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:     87
   Number with an unused Flip Flop:       8  out of     87     9%  
   Number with an unused LUT:             4  out of     87     4%  
   Number of fully used LUT-FF pairs:    75  out of     87    86%  
   Number of unique control sets:         4

IO Utilization: 
 Number of IOs:                         156
 Number of bonded IOBs:                   0  out of    200     0%  

Specific Feature Utilization:

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+--------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                              | Load  |
-----------------------------------+--------------------------------------------------------------------+-------+
S_AXI_ACLK                         | NONE(my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1)| 79    |
-----------------------------------+--------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 1.380ns (Maximum Frequency: 724.784MHz)
   Minimum input arrival time before clock: 0.947ns
   Maximum output required time after clock: 0.983ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'S_AXI_ACLK'
  Clock period: 1.380ns (frequency: 724.784MHz)
  Total number of paths / destination ports: 402 / 148
-------------------------------------------------------------------------
Delay:               1.380ns (Levels of Logic = 2)
  Source:            my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1 (FF)
  Destination:       my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i (FF)
  Source Clock:      S_AXI_ACLK rising
  Destination Clock: S_AXI_ACLK rising

  Data Path: my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1 to my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             42   0.282   0.568  my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1 (my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1)
     LUT2:I1->O            1   0.053   0.413  my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_GND_14_o_state[1]_equal_14_o1 (my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/GND_14_o_state[1]_equal_14_o)
     LUT6:I5->O            1   0.053   0.000  my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_glue_set (my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_glue_set)
     FDR:D                     0.011          my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i
    ----------------------------------------
    Total                      1.380ns (0.399ns logic, 0.981ns route)
                                       (28.9% logic, 71.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'S_AXI_ACLK'
  Total number of paths / destination ports: 97 / 75
-------------------------------------------------------------------------
Offset:              0.947ns (Levels of Logic = 3)
  Source:            S_AXI_WVALID (PAD)
  Destination:       my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1 (FF)
  Destination Clock: S_AXI_ACLK rising

  Data Path: S_AXI_WVALID to my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            1   0.053   0.413  my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1-In1 (my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1-In1)
     LUT5:I4->O            1   0.053   0.000  my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1-In3_F (N6)
     MUXF7:I0->O           2   0.214   0.000  my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1-In3 (my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1-In)
     FDR:D                     0.011          my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1
    ----------------------------------------
    Total                      0.947ns (0.534ns logic, 0.413ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'S_AXI_ACLK'
  Total number of paths / destination ports: 51 / 45
-------------------------------------------------------------------------
Offset:              0.983ns (Levels of Logic = 1)
  Source:            my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_3 (FF)
  Destination:       S_AXI_ARREADY (PAD)
  Source Clock:      S_AXI_ACLK rising

  Data Path: my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_3 to S_AXI_ARREADY
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               8   0.282   0.648  my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_3 (my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_3)
     LUT3:I0->O            0   0.053   0.000  my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/wr_done1 (S_AXI_AWREADY)
    ----------------------------------------
    Total                      0.983ns (0.335ns logic, 0.648ns route)
                                       (34.1% logic, 65.9% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock S_AXI_ACLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
S_AXI_ACLK     |    1.380|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 12.25 secs
 
--> 

Total memory usage is 282072 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   14 (   0 filtered)
Number of infos    :    6 (   0 filtered)