system_my_axi_ip_0_wrapper_xst.srp

来自「定制简单LED的IP核的设计源代码」· SRP 代码 · 共 887 行 · 第 1/4 页

Elaborating entity <my_axi_ip> (architecture <IMP>) with generics from library <my_axi_ip_v1_00_a>.

Elaborating entity <axi_lite_ipif> (architecture <imp>) with generics from library <axi_lite_ipif_v1_01_a>.

Elaborating entity <slave_attachment> (architecture <imp>) with generics from library <axi_lite_ipif_v1_01_a>.

Elaborating entity <address_decoder> (architecture <IMP>) with generics from library <axi_lite_ipif_v1_01_a>.
INFO:HDLCompiler:679 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd" Line 412. Case statement is complete. others clause is never selected
Going to verilog side to elaborate module user_logic

Elaborating module <user_logic(C_NUM_REG=1,C_SLV_DWIDTH=32)>.
WARNING:HDLCompiler:413 - "D:/_prj/Xilinx/Blog/Lab4/pcores/my_axi_ip_v1_00_a/hdl/verilog/user_logic.v" Line 119: Result of 32-bit expression is truncated to fit in 8-bit target.
Back to vhdl to continue elaboration

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <system_my_axi_ip_0_wrapper>.
    Related source file is "D:\_prj\Xilinx\Blog\Lab4\hdl\system_my_axi_ip_0_wrapper.vhd".
    Summary:
	no macro.
Unit <system_my_axi_ip_0_wrapper> synthesized.

Synthesizing Unit <my_axi_ip>.
    Related source file is "D:/_prj/Xilinx/Blog/Lab4/pcores/my_axi_ip_v1_00_a/hdl/vhdl/my_axi_ip.vhd".
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
        C_S_AXI_DATA_WIDTH = 32
        C_S_AXI_ADDR_WIDTH = 32
        C_S_AXI_MIN_SIZE = "00000000000000000000000111111111"
        C_USE_WSTRB = 0
        C_DPHASE_TIMEOUT = 8
        C_BASEADDR = "01000000000000000000000000000000"
        C_HIGHADDR = "01000000000000001111111111111111"
        C_FAMILY = "zynq"
        C_NUM_REG = 1
        C_NUM_MEM = 1
        C_SLV_AWIDTH = 32
        C_SLV_DWIDTH = 32
    Set property "MAX_FANOUT = 10000" for signal <S_AXI_ACLK>.
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
    Set property "MAX_FANOUT = 10000" for signal <S_AXI_ARESETN>.
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
INFO:Xst:3210 - "D:/_prj/Xilinx/Blog/Lab4/pcores/my_axi_ip_v1_00_a/hdl/vhdl/my_axi_ip.vhd" line 275: Output port <Bus2IP_Addr> of the instance <AXI_LITE_IPIF_I> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:/_prj/Xilinx/Blog/Lab4/pcores/my_axi_ip_v1_00_a/hdl/vhdl/my_axi_ip.vhd" line 275: Output port <Bus2IP_CS> of the instance <AXI_LITE_IPIF_I> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:/_prj/Xilinx/Blog/Lab4/pcores/my_axi_ip_v1_00_a/hdl/vhdl/my_axi_ip.vhd" line 275: Output port <Bus2IP_RNW> of the instance <AXI_LITE_IPIF_I> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <my_axi_ip> synthesized.

Synthesizing Unit <axi_lite_ipif>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/axi_lite_ipif.vhd".
        C_S_AXI_DATA_WIDTH = 32
        C_S_AXI_ADDR_WIDTH = 32
        C_S_AXI_MIN_SIZE = "00000000000000000000000111111111"
        C_USE_WSTRB = 0
        C_DPHASE_TIMEOUT = 8
        C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000001000000000000000000000000000000","0000000000000000000000000000000001000000000000001111111111111111")
        C_ARD_NUM_CE_ARRAY = (1)
        C_FAMILY = "zynq"
    Summary:
	no macro.
Unit <axi_lite_ipif> synthesized.

Synthesizing Unit <slave_attachment>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd".
        C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000001000000000000000000000000000000","0000000000000000000000000000000001000000000000001111111111111111")
        C_ARD_NUM_CE_ARRAY = (1)
        C_IPIF_ABUS_WIDTH = 32
        C_IPIF_DBUS_WIDTH = 32
        C_S_AXI_MIN_SIZE = "00000000000000000000000111111111"
        C_USE_WSTRB = 0
        C_DPHASE_TIMEOUT = 8
        C_FAMILY = "zynq"
WARNING:Xst:647 - Input <S_AXI_AWADDR<31:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_WSTRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_ARADDR<31:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd" line 336: Output port <CS_for_gaps> of the instance <I_DECODER> is unconnected or connected to loadless signal.
    Found 2-bit register for signal <state>.
    Found 2-bit register for signal <s_axi_rresp_i>.
    Found 32-bit register for signal <s_axi_rdata_i>.
    Found 1-bit register for signal <s_axi_rvalid_i>.
    Found 2-bit register for signal <s_axi_bresp_i>.
    Found 1-bit register for signal <s_axi_bvalid_i>.
    Found 4-bit register for signal <INCLUDE_DPHASE_TIMER.dpto_cnt>.
    Found 1-bit register for signal <rst>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 6                                              |
    | Outputs            | 4                                              |
    | Clock              | S_AXI_ACLK (rising_edge)                       |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | sm_idle                                        |
    | Power Up State     | sm_idle                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <INCLUDE_DPHASE_TIMER.dpto_cnt[3]_GND_14_o_add_31_OUT> created at line 502.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  43 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <slave_attachment> synthesized.

Synthesizing Unit <address_decoder>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/address_decoder.vhd".
        C_BUS_AWIDTH = 9
        C_S_AXI_MIN_SIZE = "00000000000000000000000111111111"
        C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000001000000000000000000000000000000","0000000000000000000000000000000001000000000000001111111111111111")
        C_ARD_NUM_CE_ARRAY = (1)
        C_FAMILY = "nofamily"
WARNING:Xst:647 - Input <Address_In_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus_RNW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <Bus_RNW_reg>.
    Found 1-bit register for signal <ce_out_i>.
    Found 1-bit register for signal <cs_out_i>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <address_decoder> synthesized.

Synthesizing Unit <user_logic>.
    Related source file is "D:/_prj/Xilinx/Blog/Lab4/pcores/my_axi_ip_v1_00_a/hdl/verilog/user_logic.v".
        C_NUM_REG = 1
        C_SLV_DWIDTH = 32
    Found 1-bit register for signal <slv_reg0<30>>.
    Found 1-bit register for signal <slv_reg0<29>>.
    Found 1-bit register for signal <slv_reg0<28>>.
    Found 1-bit register for signal <slv_reg0<27>>.
    Found 1-bit register for signal <slv_reg0<26>>.
    Found 1-bit register for signal <slv_reg0<25>>.
    Found 1-bit register for signal <slv_reg0<24>>.
    Found 1-bit register for signal <slv_reg0<23>>.
    Found 1-bit register for signal <slv_reg0<22>>.
    Found 1-bit register for signal <slv_reg0<21>>.
    Found 1-bit register for signal <slv_reg0<20>>.
    Found 1-bit register for signal <slv_reg0<19>>.
    Found 1-bit register for signal <slv_reg0<18>>.
    Found 1-bit register for signal <slv_reg0<17>>.
    Found 1-bit register for signal <slv_reg0<16>>.
    Found 1-bit register for signal <slv_reg0<15>>.
    Found 1-bit register for signal <slv_reg0<14>>.
    Found 1-bit register for signal <slv_reg0<13>>.
    Found 1-bit register for signal <slv_reg0<12>>.
    Found 1-bit register for signal <slv_reg0<11>>.
    Found 1-bit register for signal <slv_reg0<10>>.
    Found 1-bit register for signal <slv_reg0<9>>.
    Found 1-bit register for signal <slv_reg0<8>>.
    Found 1-bit register for signal <slv_reg0<7>>.
    Found 1-bit register for signal <slv_reg0<6>>.
    Found 1-bit register for signal <slv_reg0<5>>.
    Found 1-bit register for signal <slv_reg0<4>>.
    Found 1-bit register for signal <slv_reg0<3>>.
    Found 1-bit register for signal <slv_reg0<2>>.
    Found 1-bit register for signal <slv_reg0<1>>.
    Found 1-bit register for signal <slv_reg0<0>>.
    Found 1-bit register for signal <slv_reg0<31>>.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred  35 Multiplexer(s).
Unit <user_logic> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 4-bit adder                                           : 1
# Registers                                            : 35
 1-bit register                                        : 30
 2-bit register                                        : 2
 32-bit register                                       : 1
 4-bit register                                        : 1
 8-bit register                                        : 1
# Multiplexers                                         : 37
 1-bit 2-to-1 multiplexer                              : 33
 32-bit 2-to-1 multiplexer                             : 4
# FSMs                                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <slave_attachment>.
The following registers are absorbed into counter <INCLUDE_DPHASE_TIMER.dpto_cnt>: 1 register on signal <INCLUDE_DPHASE_TIMER.dpto_cnt>.
Unit <slave_attachment> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 4-bit up counter                                      : 1
# Registers                                            : 74
 Flip-Flops                                            : 74
# Multiplexers                                         : 37
 1-bit 2-to-1 multiplexer                              : 33
 32-bit 2-to-1 multiplexer                             : 4
# FSMs                                                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch <s_axi_rresp_i_0> has a constant value of 0 in block <slave_attachment>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <s_axi_bresp_i_0> has a constant value of 0 in block <slave_attachment>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <I_DECODER/ce_out_i_0> in Unit <slave_attachment> is equivalent to the following FF/Latch, which will be removed : <I_DECODER/cs_out_i_0> 
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/FSM_0> on signal <state[1:2]> with user encoding.
----------------------
 State    | Encoding
----------------------
 sm_idle  | 00
 sm_read  | 01