📄 system_map.map
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Release 14.2 Map P.28xd (nt)Xilinx Map Application Log File for Design 'system'Design Information------------------Command Line : map -o system_map.ncd -w -pr b -ol high -timing -detail
system.ngd system.pcf Target Device : xc7z020Target Package : clg484Target Speed : -1Mapper Version : zynq -- $Revision: 1.55 $Mapped Date : Tue Oct 09 18:56:46 2012WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB" has an undefined
IOSTANDARD.WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB" is not constrained
(LOC) to a specific location.WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK" has an undefined
IOSTANDARD.WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK" is not constrained
(LOC) to a specific location.WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB" has an undefined
IOSTANDARD.WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB" is not constrained
(LOC) to a specific location.Mapping design into LUTs...Writing file system_map.ngm...Running directed packing...Running delay-based LUT packing...Updating timing models...INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).Running timing-driven placement...Total REAL time at the beginning of Placer: 30 secs Total CPU time at the beginning of Placer: 25 secs Phase 1.1 Initial Placement AnalysisPhase 1.1 Initial Placement Analysis (Checksum:eef39f90) REAL time: 32 secs Phase 2.7 Design Feasibility CheckPhase 2.7 Design Feasibility Check (Checksum:eef39f90) REAL time: 32 secs Phase 3.31 Local Placement OptimizationPhase 3.31 Local Placement Optimization (Checksum:eef39f90) REAL time: 32 secs Phase 4.2 Initial Placement for Architecture Specific FeaturesPhase 4.2 Initial Placement for Architecture Specific Features
(Checksum:c8dd9f40) REAL time: 37 secs Phase 5.30 Global Clock Region AssignmentPhase 5.30 Global Clock Region Assignment (Checksum:c8dd9f40) REAL time: 37 secs Phase 6.3 Local Placement OptimizationPhase 6.3 Local Placement Optimization (Checksum:c8dd9f40) REAL time: 37 secs Phase 7.5 Local Placement OptimizationPhase 7.5 Local Placement Optimization (Checksum:c8dd9f40) REAL time: 37 secs Phase 8.8 Global Placement..................................................................................................................................................................................................................................................................................................Phase 8.8 Global Placement (Checksum:e7798f31) REAL time: 38 secs Phase 9.5 Local Placement OptimizationPhase 9.5 Local Placement Optimization (Checksum:e7798f31) REAL time: 38 secs Phase 10.18 Placement OptimizationPhase 10.18 Placement Optimization (Checksum:bd21f42d) REAL time: 39 secs Phase 11.5 Local Placement OptimizationPhase 11.5 Local Placement Optimization (Checksum:bd21f42d) REAL time: 39 secs Phase 12.34 Placement ValidationPhase 12.34 Placement Validation (Checksum:bd21f42d) REAL time: 39 secs Total REAL time to Placer completion: 39 secs Total CPU time to Placer completion: 33 secs Running post-placement packing...Writing output files...Design Summary--------------Design Summary:Number of errors: 0Number of warnings: 6Slice Logic Utilization: Number of Slice Registers: 152 out of 106,400 1% Number used as Flip Flops: 152 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 220 out of 53,200 1% Number used as logic: 220 out of 53,200 1% Number using O6 output only: 189 Number using O5 output only: 0 Number using O5 and O6: 31 Number used as ROM: 0 Number used as Memory: 0 out of 17,400 0% Number used exclusively as route-thrus: 0Slice Logic Distribution: Number of occupied Slices: 74 out of 13,300 1% Number of LUT Flip Flop pairs used: 229 Number with an unused Flip Flop: 81 out of 229 35% Number with an unused LUT: 9 out of 229 3% Number of fully used LUT-FF pairs: 139 out of 229 60% Number of unique control sets: 12 Number of slice register sites lost to control set restrictions: 40 out of 106,400 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails.IO Utilization: Number of bonded IOBs: 8 out of 200 4% Number of LOCed IOBs: 8 out of 8 100% Number of bonded IOPAD: 130 out of 130 100%Specific Feature Utilization: Number of RAMB36E1/FIFO36E1s: 0 out of 140 0% Number of RAMB18E1/FIFO18E1s: 0 out of 280 0% Number of BUFG/BUFGCTRLs: 1 out of 32 3% Number used as BUFGs: 1 Number used as BUFGCTRLs: 0 Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 200 0% Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 200 0% Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0 Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 200 0% Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 16 0% Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 16 0% Number of BSCANs: 0 out of 4 0% Number of BUFHCEs: 0 out of 72 0% Number of BUFRs: 0 out of 16 0% Number of CAPTUREs: 0 out of 1 0% Number of DNA_PORTs: 0 out of 1 0% Number of DSP48E1s: 0 out of 220 0% Number of EFUSE_USRs: 0 out of 1 0% Number of FRAME_ECCs: 0 out of 1 0% Number of ICAPs: 0 out of 2 0% Number of IDELAYCTRLs: 0 out of 4 0% Number of IN_FIFOs: 0 out of 16 0% Number of MMCME2_ADVs: 0 out of 4 0% Number of OUT_FIFOs: 0 out of 16 0% Number of PHASER_REFs: 0 out of 4 0% Number of PHY_CONTROLs: 0 out of 4 0% Number of PLLE2_ADVs: 0 out of 4 0% Number of PS7s: 1 out of 1 100% Number of STARTUPs: 0 out of 1 0% Number of XADCs: 0 out of 1 0%Average Fanout of Non-Clock Nets: 2.41Peak Memory Usage: 518 MBTotal REAL time to MAP completion: 41 secs Total CPU time to MAP completion: 34 secs Mapping completed.See MAP report file "system_map.mrp" for details.⌨️ 快捷键说明
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