📄 system.pcf
字号:
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_10"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_9"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_8"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_7"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_6"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_5"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_4"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_3"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_2"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_1"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_0"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cnt_3"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cnt_2"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cnt_1"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cnt_0"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/write_cs_FSM_FFd1"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/write_cs_FSM_FFd2"
BEL
"axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axilite.gen_axilite_conv.axilite_conv_inst/write_active"
BEL
"axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axilite.gen_axilite_conv.axilite_conv_inst/read_active"
BEL
"axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axilite.gen_axilite_conv.axilite_conv_inst/busy"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_grant_hot_i_0"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_valid_i"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/s_axi_rlast_i"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/s_axi_arready_i"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/read_cs_0"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.gen_decerr.decerr_slave_inst/s_axi_awready_i"
BEL
"axi_interconnect_1/axi_interconnect_1/mi_register_slice_bank/gen_reg_slot[0].register_slice_inst/reset"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/reset"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/s_ready_i_0"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/grant_rnw"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_aw/m_ready_d_2"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_aw/m_ready_d_1"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_aw/m_ready_d_0"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_ar/m_ready_d_1"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.splitter_ar/m_ready_d_0"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/m_atarget_enc_0_1"
BEL
"axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/grant_rnw_1"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd2"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_31"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_30"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_29"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_28"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_27"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_26"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_25"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_24"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_23"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_22"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_21"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_20"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_19"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_18"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_17"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_16"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_15"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_14"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_13"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_12"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_11"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_10"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_9"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_8"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_7"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_6"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_5"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_4"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_3"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_2"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_1"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_0"
BEL "my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_7" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_6" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_5" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_4" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_3" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_2" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_1" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_0" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_31" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_8" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_9" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_10" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_11" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_12" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_13" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_14" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_15" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_16" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_17" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_19" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_20" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_18" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_21" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_22" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_23" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_24" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_25" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_26" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_27" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_28" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_29" BEL
"my_axi_ip_0/my_axi_ip_0/USER_LOGIC_I/slv_reg0_30" BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg"
BEL "my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/ce_out_i_0"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_3"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_2"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_1"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_0"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/ce_out_i_0_1"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd1_1"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_1"
BEL
"my_axi_ip_0/my_axi_ip_0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_FSM_FFd2_1"
PIN "processing_system7_0/processing_system7_0/PS7_i_pins<357>";
TIMEGRP axi_interconnect_1_reset_resync = BEL
"axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2"
BEL
"axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1"
BEL
"axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_0";
TIMEGRP axi_interconnect_1_reset_source = FFS(*) PADS(*);
PATH TS_axi_interconnect_1_reset_resync_path = FROM TIMEGRP
"axi_interconnect_1_reset_source" TO TIMEGRP
"axi_interconnect_1_reset_resync";
PATH "TS_axi_interconnect_1_reset_resync_path" TIG;
TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_0" 50 MHz HIGH 50%;
SCHEMATIC END;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -