system.pcf

定制简单LED的IP核的设计源代码

//! **************************************************************************
// Written by: Map P.28xd on Tue Oct 09 18:57:26 2012
//! **************************************************************************

SCHEMATIC START;
COMP "processing_system7_0_MIO<6>" LOCATE = SITE "A4" LEVEL 1;
COMP "processing_system7_0_MIO<5>" LOCATE = SITE "A3" LEVEL 1;
COMP "processing_system7_0_MIO<8>" LOCATE = SITE "E5" LEVEL 1;
COMP "processing_system7_0_MIO<7>" LOCATE = SITE "D5" LEVEL 1;
COMP "processing_system7_0_MIO<9>" LOCATE = SITE "C4" LEVEL 1;
COMP "processing_system7_0_MIO<0>" LOCATE = SITE "G6" LEVEL 1;
COMP "processing_system7_0_MIO<2>" LOCATE = SITE "A2" LEVEL 1;
COMP "processing_system7_0_MIO<1>" LOCATE = SITE "A1" LEVEL 1;
COMP "processing_system7_0_MIO<4>" LOCATE = SITE "E4" LEVEL 1;
COMP "processing_system7_0_MIO<3>" LOCATE = SITE "F6" LEVEL 1;
COMP "processing_system7_0_DDR_ODT" LOCATE = SITE "P5" LEVEL 1;
COMP "processing_system7_0_DDR_DQS_n<0>" LOCATE = SITE "D2" LEVEL 1;
COMP "processing_system7_0_DDR_DQS_n<1>" LOCATE = SITE "J2" LEVEL 1;
COMP "processing_system7_0_DDR_DQS_n<2>" LOCATE = SITE "P2" LEVEL 1;
COMP "processing_system7_0_DDR_DQS_n<3>" LOCATE = SITE "W2" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<9>" LOCATE = SITE "H5" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<8>" LOCATE = SITE "J5" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<7>" LOCATE = SITE "J6" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<6>" LOCATE = SITE "J7" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<5>" LOCATE = SITE "K5" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<4>" LOCATE = SITE "K6" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<3>" LOCATE = SITE "L4" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<2>" LOCATE = SITE "K4" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<1>" LOCATE = SITE "M5" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<0>" LOCATE = SITE "M4" LEVEL 1;
COMP "processing_system7_0_DDR_WEB_pin" LOCATE = SITE "R4" LEVEL 1;
COMP "LD<0>" LOCATE = SITE "T22" LEVEL 1;
COMP "LD<1>" LOCATE = SITE "T21" LEVEL 1;
COMP "LD<2>" LOCATE = SITE "U22" LEVEL 1;
COMP "LD<3>" LOCATE = SITE "U21" LEVEL 1;
COMP "LD<4>" LOCATE = SITE "V22" LEVEL 1;
COMP "LD<5>" LOCATE = SITE "W22" LEVEL 1;
COMP "LD<6>" LOCATE = SITE "U19" LEVEL 1;
COMP "LD<7>" LOCATE = SITE "U14" LEVEL 1;
COMP "processing_system7_0_DDR_DQS<0>" LOCATE = SITE "C2" LEVEL 1;
COMP "processing_system7_0_DDR_CAS_n" LOCATE = SITE "P3" LEVEL 1;
COMP "processing_system7_0_DDR_DQS<3>" LOCATE = SITE "V2" LEVEL 1;
COMP "processing_system7_0_DDR_DQS<2>" LOCATE = SITE "N2" LEVEL 1;
COMP "processing_system7_0_DDR_DQS<1>" LOCATE = SITE "H2" LEVEL 1;
COMP "processing_system7_0_DDR_RAS_n" LOCATE = SITE "R5" LEVEL 1;
COMP "processing_system7_0_DDR_BankAddr<1>" LOCATE = SITE "L6" LEVEL 1;
COMP "processing_system7_0_DDR_BankAddr<2>" LOCATE = SITE "M6" LEVEL 1;
COMP "processing_system7_0_DDR_BankAddr<0>" LOCATE = SITE "L7" LEVEL 1;
COMP "processing_system7_0_DDR_Clk" LOCATE = SITE "N4" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<0>" LOCATE = SITE "D1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<4>" LOCATE = SITE "E3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<3>" LOCATE = SITE "D3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<2>" LOCATE = SITE "B2" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<1>" LOCATE = SITE "C3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<8>" LOCATE = SITE "G2" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<7>" LOCATE = SITE "F1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<6>" LOCATE = SITE "F2" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<5>" LOCATE = SITE "E1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<9>" LOCATE = SITE "G1" LEVEL 1;
COMP "processing_system7_0_MIO<50>" LOCATE = SITE "D13" LEVEL 1;
COMP "processing_system7_0_MIO<52>" LOCATE = SITE "D10" LEVEL 1;
COMP "processing_system7_0_MIO<51>" LOCATE = SITE "C10" LEVEL 1;
COMP "processing_system7_0_MIO<53>" LOCATE = SITE "C12" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<30>" LOCATE = SITE "W3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<31>" LOCATE = SITE "Y1" LEVEL 1;
COMP "processing_system7_0_DDR_VRN" LOCATE = SITE "M7" LEVEL 1;
COMP "processing_system7_0_DDR_VRP" LOCATE = SITE "N7" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<20>" LOCATE = SITE "R3" LEVEL 1;
COMP "processing_system7_0_DDR_Clk_n" LOCATE = SITE "N5" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<24>" LOCATE = SITE "AA3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<23>" LOCATE = SITE "R1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<22>" LOCATE = SITE "M2" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<21>" LOCATE = SITE "T2" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<28>" LOCATE = SITE "W1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<27>" LOCATE = SITE "U2" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<26>" LOCATE = SITE "AA1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<25>" LOCATE = SITE "U1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<29>" LOCATE = SITE "Y3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<10>" LOCATE = SITE "L1" LEVEL 1;
COMP "processing_system7_0_DDR_CS_n" LOCATE = SITE "P6" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<14>" LOCATE = SITE "J1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<13>" LOCATE = SITE "K1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<12>" LOCATE = SITE "L3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<11>" LOCATE = SITE "L2" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<18>" LOCATE = SITE "N3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<17>" LOCATE = SITE "T3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<16>" LOCATE = SITE "M1" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<15>" LOCATE = SITE "K3" LEVEL 1;
COMP "processing_system7_0_DDR_DQ<19>" LOCATE = SITE "T1" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<13>" LOCATE = SITE "F4" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<14>" LOCATE = SITE "G4" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<11>" LOCATE = SITE "G5" LEVEL 1;
COMP "processing_system7_0_DDR_CKE" LOCATE = SITE "V3" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<12>" LOCATE = SITE "H4" LEVEL 1;
COMP "processing_system7_0_DDR_Addr<10>" LOCATE = SITE "J3" LEVEL 1;
COMP "processing_system7_0_MIO<26>" LOCATE = SITE "A13" LEVEL 1;
COMP "processing_system7_0_MIO<25>" LOCATE = SITE "F12" LEVEL 1;
COMP "processing_system7_0_MIO<28>" LOCATE = SITE "A12" LEVEL 1;
COMP "processing_system7_0_MIO<27>" LOCATE = SITE "D7" LEVEL 1;
COMP "processing_system7_0_MIO<29>" LOCATE = SITE "E8" LEVEL 1;
COMP "processing_system7_0_MIO<20>" LOCATE = SITE "A8" LEVEL 1;
COMP "processing_system7_0_MIO<22>" LOCATE = SITE "A14" LEVEL 1;
COMP "processing_system7_0_MIO<21>" LOCATE = SITE "F11" LEVEL 1;
COMP "processing_system7_0_MIO<24>" LOCATE = SITE "B7" LEVEL 1;
COMP "processing_system7_0_MIO<23>" LOCATE = SITE "E11" LEVEL 1;
COMP "processing_system7_0_MIO<16>" LOCATE = SITE "D6" LEVEL 1;
COMP "processing_system7_0_MIO<15>" LOCATE = SITE "E6" LEVEL 1;
COMP "processing_system7_0_MIO<18>" LOCATE = SITE "A7" LEVEL 1;
COMP "processing_system7_0_MIO<17>" LOCATE = SITE "E9" LEVEL 1;
COMP "processing_system7_0_MIO<19>" LOCATE = SITE "E10" LEVEL 1;
COMP "processing_system7_0_MIO<10>" LOCATE = SITE "G7" LEVEL 1;
COMP "processing_system7_0_MIO<12>" LOCATE = SITE "C5" LEVEL 1;
COMP "processing_system7_0_MIO<11>" LOCATE = SITE "B4" LEVEL 1;
COMP "processing_system7_0_MIO<14>" LOCATE = SITE "B6" LEVEL 1;
COMP "processing_system7_0_MIO<13>" LOCATE = SITE "A6" LEVEL 1;
COMP "processing_system7_0_DDR_DRSTB" LOCATE = SITE "F3" LEVEL 1;
COMP "processing_system7_0_MIO<46>" LOCATE = SITE "D12" LEVEL 1;
COMP "processing_system7_0_MIO<45>" LOCATE = SITE "B9" LEVEL 1;
COMP "processing_system7_0_MIO<48>" LOCATE = SITE "D11" LEVEL 1;
COMP "processing_system7_0_MIO<47>" LOCATE = SITE "B10" LEVEL 1;
COMP "processing_system7_0_MIO<49>" LOCATE = SITE "C14" LEVEL 1;
COMP "processing_system7_0_MIO<40>" LOCATE = SITE "E14" LEVEL 1;
COMP "processing_system7_0_MIO<42>" LOCATE = SITE "D8" LEVEL 1;
COMP "processing_system7_0_MIO<41>" LOCATE = SITE "C8" LEVEL 1;
COMP "processing_system7_0_MIO<44>" LOCATE = SITE "E13" LEVEL 1;
COMP "processing_system7_0_MIO<43>" LOCATE = SITE "B11" LEVEL 1;
COMP "processing_system7_0_MIO<36>" LOCATE = SITE "A9" LEVEL 1;
COMP "processing_system7_0_MIO<35>" LOCATE = SITE "F14" LEVEL 1;
COMP "processing_system7_0_MIO<38>" LOCATE = SITE "F13" LEVEL 1;
COMP "processing_system7_0_MIO<37>" LOCATE = SITE "B14" LEVEL 1;
COMP "processing_system7_0_MIO<39>" LOCATE = SITE "C13" LEVEL 1;
COMP "processing_system7_0_MIO<30>" LOCATE = SITE "A11" LEVEL 1;
COMP "processing_system7_0_MIO<32>" LOCATE = SITE "C7" LEVEL 1;
COMP "processing_system7_0_MIO<31>" LOCATE = SITE "F9" LEVEL 1;
COMP "processing_system7_0_MIO<34>" LOCATE = SITE "B12" LEVEL 1;
COMP "processing_system7_0_MIO<33>" LOCATE = SITE "G13" LEVEL 1;
COMP "processing_system7_0_DDR_DM<0>" LOCATE = SITE "B1" LEVEL 1;
COMP "processing_system7_0_DDR_DM<3>" LOCATE = SITE "AA2" LEVEL 1;
COMP "processing_system7_0_DDR_DM<2>" LOCATE = SITE "P1" LEVEL 1;
COMP "processing_system7_0_DDR_DM<1>" LOCATE = SITE "H3" LEVEL 1;
PIN processing_system7_0/processing_system7_0/PS7_i_pins<357> = BEL
        "processing_system7_0/processing_system7_0/PS7_i" PINNAME MAXIGP0ACLK;
TIMEGRP clk_fpga_0 = BEL
        "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_pipe_2"
        BEL
        "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_pipe_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_pipe_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2"
        BEL
        "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axilite.gen_axilite_conv.axilite_conv_inst/areset_d_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/mi_converter_bank/gen_conv_slot[0].clock_conv_inst/m_axi_reset_out_n_i"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/m_atarget_enc_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/m_atarget_hot_1"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/m_atarget_hot_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/s_awvalid_reg_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/s_arvalid_reg_0"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_53"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_52"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_47"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_46"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_45"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_44"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_43"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_42"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_41"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_40"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_39"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_38"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_37"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_36"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_35"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_34"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_33"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_32"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_31"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_30"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_29"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_28"
        BEL
        "axi_interconnect_1/axi_interconnect_1/crossbar_samd/gen_sasd.crossbar_sasd_0/gen_crossbar.addr_arbiter_inst/m_amesg_i_11"