led.fit.rpt

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

Fitter report for LED
Sun May 04 16:01:27 2008
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Resource Usage Summary
  5. Input Pins
  6. Output Pins
  7. I/O Bank Usage
  8. All Package Pins
  9. Output Pin Default Load For Reported TCO
 10. Fitter Resource Utilization by Entity
 11. Delay Chain Summary
 12. Pad To Core Delay Chain Fanout
 13. Control Signals
 14. Global & Other Fast Signals
 15. Non-Global High Fan-Out Signals
 16. Fitter RAM Summary
 17. Fitter Device Options
 18. Advanced Data - General
 19. Advanced Data - Placement Preparation
 20. Fitter Messages
 21. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Fitter Summary                                                        ;
+-----------------------+-----------------------------------------------+
; Fitter Status         ; Failed - Sun May 04 16:01:27 2008             ;
; Quartus II Version    ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name         ; LED                                           ;
; Top-level Entity Name ; Block1                                        ;
; Family                ; Cyclone                                       ;
; Device                ; EP1C3T144C8                                   ;
; Timing Models         ; Final                                         ;
; Total logic elements  ; 1,724 / 2,910 ( 59 % )                        ;
; Total pins            ; 51 / 104 ( 49 % )                             ;
; Total virtual pins    ; 0                                             ;
; Total memory bits     ; 56,320 / 59,904 ( 94 % )                      ;
; Total PLLs            ; 0 / 1 ( 0 % )                                 ;
+-----------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP1C3T144C8                    ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;