stp1.stp

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

<session jtag_chain="ByteBlasterII [LPT1]" jtag_device="@1: EP1C3 (0x020810DD)" sof_file="" top_level_entity="Block1">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <global_info>
    <multi attribute="window position" size="9" value="930,568,398,174,0,50,0,0,0"/>
    <single attribute="active instance" value="0"/>
    <single attribute="lock mode" value="36110"/>
    <multi attribute="column width" size="18" value="34,34,140,74,68,70,88,182,101,101,101,101,101,101,101,101,107,78"/>
  </global_info>
  <instance compilation_mode="full" entity_name="sld_signaltap" is_auto_node="yes" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
    <position_info>
      <single attribute="active tab" value="0"/>
      <single attribute="data vertical scroll position" value="0"/>
      <single attribute="data horizontal scroll position" value="0"/>
      <single attribute="zoom level numerator" value="1"/>
      <single attribute="zoom level denominator" value="1"/>
      <single attribute="zoom offset numerator" value="130048"/>
      <single attribute="zoom offset denominator" value="1"/>
      <single attribute="setup vertical scroll position" value="0"/>
      <single attribute="setup horizontal scroll position" value="18"/>
    </position_info>
    <signal_set global_temp="1" name="signal_set: 2008/05/03 22:56:30  #0">
      <clock name="clk" polarity="posedge" tap_mode="classic"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="yes" trigger_in_node="clk" trigger_in_tap_mode="classic" trigger_out_enable="yes" trigger_out_pin="auto_stp_trigger_out_0"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="AD[0]" tap_mode="classic" type="input pin"/>
          <wire name="AD[1]" tap_mode="classic" type="input pin"/>
          <wire name="AD[2]" tap_mode="classic" type="input pin"/>
          <wire name="AD[3]" tap_mode="classic" type="input pin"/>
          <wire name="AD[4]" tap_mode="classic" type="input pin"/>
          <wire name="AD[5]" tap_mode="classic" type="input pin"/>
          <wire name="AD[6]" tap_mode="classic" type="input pin"/>
          <wire name="AD[7]" tap_mode="classic" type="input pin"/>
          <wire name="ADclk" tap_mode="classic" type="output pin"/>
          <wire name="DAC[0]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[1]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[2]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[3]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[4]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[5]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[6]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[7]" tap_mode="classic" type="output pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="AD[0]" tap_mode="classic" type="input pin"/>
          <wire name="AD[1]" tap_mode="classic" type="input pin"/>
          <wire name="AD[2]" tap_mode="classic" type="input pin"/>
          <wire name="AD[3]" tap_mode="classic" type="input pin"/>
          <wire name="AD[4]" tap_mode="classic" type="input pin"/>
          <wire name="AD[5]" tap_mode="classic" type="input pin"/>
          <wire name="AD[6]" tap_mode="classic" type="input pin"/>
          <wire name="AD[7]" tap_mode="classic" type="input pin"/>
          <wire name="ADclk" tap_mode="classic" type="output pin"/>
          <wire name="DAC[0]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[1]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[2]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[3]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[4]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[5]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[6]" tap_mode="classic" type="output pin"/>
          <wire name="DAC[7]" tap_mode="classic" type="output pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="AD[7..0]" order="lsb_to_msb" radix="line" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="AD[0]"/>
            <net is_signal_inverted="no" name="AD[1]"/>
            <net is_signal_inverted="no" name="AD[2]"/>
            <net is_signal_inverted="no" name="AD[3]"/>
            <net is_signal_inverted="no" name="AD[4]"/>
            <net is_signal_inverted="no" name="AD[5]"/>
            <net is_signal_inverted="no" name="AD[6]"/>
            <net is_signal_inverted="no" name="AD[7]"/>
          </bus>
          <net is_signal_inverted="no" name="ADclk"/>
          <bus is_signal_inverted="no" link="all" name="DAC" order="lsb_to_msb" radix="line" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="DAC[0]"/>
            <net is_signal_inverted="no" name="DAC[1]"/>
            <net is_signal_inverted="no" name="DAC[2]"/>
            <net is_signal_inverted="no" name="DAC[3]"/>
            <net is_signal_inverted="no" name="DAC[4]"/>
            <net is_signal_inverted="no" name="DAC[5]"/>
            <net is_signal_inverted="no" name="DAC[6]"/>
            <net is_signal_inverted="no" name="DAC[7]"/>
          </bus>
        </data_view>
        <setup_view>
          <bus is_signal_inverted="no" link="all" name="AD[7..0]" order="lsb_to_msb" radix="line" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="AD[0]"/>
            <net is_signal_inverted="no" name="AD[1]"/>
            <net is_signal_inverted="no" name="AD[2]"/>
            <net is_signal_inverted="no" name="AD[3]"/>
            <net is_signal_inverted="no" name="AD[4]"/>
            <net is_signal_inverted="no" name="AD[5]"/>
            <net is_signal_inverted="no" name="AD[6]"/>
            <net is_signal_inverted="no" name="AD[7]"/>
          </bus>
          <net is_signal_inverted="no" name="ADclk"/>
          <bus is_signal_inverted="no" link="all" name="DAC" order="lsb_to_msb" radix="line" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="DAC[0]"/>
            <net is_signal_inverted="no" name="DAC[1]"/>
            <net is_signal_inverted="no" name="DAC[2]"/>
            <net is_signal_inverted="no" name="DAC[3]"/>
            <net is_signal_inverted="no" name="DAC[4]"/>
            <net is_signal_inverted="no" name="DAC[5]"/>
            <net is_signal_inverted="no" name="DAC[6]"/>
            <net is_signal_inverted="no" name="DAC[7]"/>
          </bus>
        </setup_view>
      </presentation>
      <trigger CRC="94F97B55" global_temp="1" name="trigger: 2008/05/03 22:56:30  #1" position="center" power_up_trigger_mode="false" segment_size="1" trigger_in="rising edge" trigger_out="active high" trigger_type="circular">
        <power_up_trigger position="pre" trigger_in="dont_care" trigger_out="active high"/>
        <events use_custom_flow_control="no">
          <level enabled="yes" name="condition1" type="basic">
            <power_up enabled="yes">
            </power_up>
            <op_node/>
          </level>
        </events>
      </trigger>
    </signal_set>
  </instance>
  <mnemonics/>
  <static_plugin_mnemonics/>
</session>