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cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

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--GENERATION: STANDARD
--VERSION: WM1.0


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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Data_s1_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_data_master_address_to_slave : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
                 signal cpu_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_data_master_read : IN STD_LOGIC;
                 signal cpu_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_data_master_write : IN STD_LOGIC;
                 signal cpu_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal Data_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal Data_s1_chipselect : OUT STD_LOGIC;
                 signal Data_s1_reset_n : OUT STD_LOGIC;
                 signal Data_s1_write_n : OUT STD_LOGIC;
                 signal Data_s1_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal cpu_data_master_granted_Data_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_qualified_request_Data_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_read_data_valid_Data_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_requests_Data_s1 : OUT STD_LOGIC;
                 signal d1_Data_s1_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of Data_s1_arbitrator : entity is FALSE;
end entity Data_s1_arbitrator;


architecture europa of Data_s1_arbitrator is
                signal Data_s1_allgrants :  STD_LOGIC;
                signal Data_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal Data_s1_any_bursting_master_saved_grant :  STD_LOGIC;
                signal Data_s1_any_continuerequest :  STD_LOGIC;
                signal Data_s1_arb_counter_enable :  STD_LOGIC;
                signal Data_s1_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal Data_s1_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal Data_s1_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal Data_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal Data_s1_begins_xfer :  STD_LOGIC;
                signal Data_s1_end_xfer :  STD_LOGIC;
                signal Data_s1_firsttransfer :  STD_LOGIC;
                signal Data_s1_grant_vector :  STD_LOGIC;
                signal Data_s1_in_a_read_cycle :  STD_LOGIC;
                signal Data_s1_in_a_write_cycle :  STD_LOGIC;
                signal Data_s1_master_qreq_vector :  STD_LOGIC;
                signal Data_s1_non_bursting_master_requests :  STD_LOGIC;
                signal Data_s1_pretend_byte_enable :  STD_LOGIC;
                signal Data_s1_reg_firsttransfer :  STD_LOGIC;
                signal Data_s1_slavearbiterlockenable :  STD_LOGIC;
                signal Data_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal Data_s1_unreg_firsttransfer :  STD_LOGIC;
                signal Data_s1_waits_for_read :  STD_LOGIC;
                signal Data_s1_waits_for_write :  STD_LOGIC;
                signal cpu_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_data_master_continuerequest :  STD_LOGIC;
                signal cpu_data_master_saved_grant_Data_s1 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal enable_nonzero_assertions :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_Data_s1 :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_cpu_data_master_granted_Data_s1 :  STD_LOGIC;
                signal internal_cpu_data_master_qualified_request_Data_s1 :  STD_LOGIC;
                signal internal_cpu_data_master_requests_Data_s1 :  STD_LOGIC;
                signal shifted_address_to_Data_s1_from_cpu_data_master :  STD_LOGIC_VECTOR (13 DOWNTO 0);
                signal wait_for_Data_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT Data_s1_end_xfer;
      end if;
    end if;

  end process;

  Data_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_cpu_data_master_qualified_request_Data_s1);
  internal_cpu_data_master_requests_Data_s1 <= ((to_std_logic(((Std_Logic_Vector'(cpu_data_master_address_to_slave(13 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("10000000110000")))) AND ((cpu_data_master_read OR cpu_data_master_write)))) AND cpu_data_master_write;
  --Data_s1_arb_share_counter set values, which is an e_mux
  Data_s1_arb_share_set_values <= std_logic_vector'("01");
  --Data_s1_non_bursting_master_requests mux, which is an e_mux
  Data_s1_non_bursting_master_requests <= internal_cpu_data_master_requests_Data_s1;
  --Data_s1_any_bursting_master_saved_grant mux, which is an e_mux
  Data_s1_any_bursting_master_saved_grant <= std_logic'('0');
  --Data_s1_arb_share_counter_next_value assignment, which is an e_assign
  Data_s1_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(Data_s1_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (Data_s1_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(Data_s1_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (Data_s1_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --Data_s1_allgrants all slave grants, which is an e_mux
  Data_s1_allgrants <= Data_s1_grant_vector;
  --Data_s1_end_xfer assignment, which is an e_assign
  Data_s1_end_xfer <= NOT ((Data_s1_waits_for_read OR Data_s1_waits_for_write));
  --end_xfer_arb_share_counter_term_Data_s1 arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_Data_s1 <= Data_s1_end_xfer AND (((NOT Data_s1_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --Data_s1_arb_share_counter arbitration counter enable, which is an e_assign
  Data_s1_arb_counter_enable <= ((end_xfer_arb_share_counter_term_Data_s1 AND Data_s1_allgrants)) OR ((end_xfer_arb_share_counter_term_Data_s1 AND NOT Data_s1_non_bursting_master_requests));
  --Data_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      Data_s1_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(Data_s1_arb_counter_enable) = '1' then 
        Data_s1_arb_share_counter <= Data_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --Data_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      Data_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((Data_s1_master_qreq_vector AND end_xfer_arb_share_counter_term_Data_s1)) OR ((end_xfer_arb_share_counter_term_Data_s1 AND NOT Data_s1_non_bursting_master_requests)))) = '1' then 
        Data_s1_slavearbiterlockenable <= or_reduce(Data_s1_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --cpu/data_master Data/s1 arbiterlock, which is an e_assign
  cpu_data_master_arbiterlock <= Data_s1_slavearbiterlockenable AND cpu_data_master_continuerequest;
  --Data_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  Data_s1_slavearbiterlockenable2 <= or_reduce(Data_s1_arb_share_counter_next_value);
  --cpu/data_master Data/s1 arbiterlock2, which is an e_assign
  cpu_data_master_arbiterlock2 <= Data_s1_slavearbiterlockenable2 AND cpu_data_master_continuerequest;
  --Data_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  Data_s1_any_continuerequest <= std_logic'('1');
  --cpu_data_master_continuerequest continued request, which is an e_assign
  cpu_data_master_continuerequest <= std_logic'('1');
  internal_cpu_data_master_qualified_request_Data_s1 <= internal_cpu_data_master_requests_Data_s1 AND NOT (((NOT cpu_data_master_waitrequest) AND cpu_data_master_write));
  --Data_s1_writedata mux, which is an e_mux
  Data_s1_writedata <= cpu_data_master_writedata (7 DOWNTO 0);
  --master is always granted when requested
  internal_cpu_data_master_granted_Data_s1 <= internal_cpu_data_master_qualified_request_Data_s1;
  --cpu/data_master saved-grant Data/s1, which is an e_assign
  cpu_data_master_saved_grant_Data_s1 <= internal_cpu_data_master_requests_Data_s1;
  --allow new arb cycle for Data/s1, which is an e_assign
  Data_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  Data_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  Data_s1_master_qreq_vector <= std_logic'('1');
  --Data_s1_reset_n assignment, which is an e_assign
  Data_s1_reset_n <= reset_n;
  Data_s1_chipselect <= internal_cpu_data_master_granted_Data_s1;
  --Data_s1_firsttransfer first transaction, which is an e_assign
  Data_s1_firsttransfer <= A_WE_StdLogic((std_logic'(Data_s1_begins_xfer) = '1'), Data_s1_unreg_firsttransfer, Data_s1_reg_firsttransfer);
  --Data_s1_unreg_firsttransfer first transaction, which is an e_assign
  Data_s1_unreg_firsttransfer <= NOT ((Data_s1_slavearbiterlockenable AND Data_s1_any_continuerequest));
  --Data_s1_reg_firsttransfer first transaction, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      Data_s1_reg_firsttransfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if std_logic'(Data_s1_begins_xfer) = '1' then 
        Data_s1_reg_firsttransfer <= Data_s1_unreg_firsttransfer;
      end if;
    end if;

  end process;

  --Data_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  Data_s1_beginbursttransfer_internal <= Data_s1_begins_xfer;
  --~Data_s1_write_n assignment, which is an e_mux
  Data_s1_write_n <= NOT ((((internal_cpu_data_master_granted_Data_s1 AND cpu_data_master_write)) AND Data_s1_pretend_byte_enable));
  shifted_address_to_Data_s1_from_cpu_data_master <= cpu_data_master_address_to_slave;
  --Data_s1_address mux, which is an e_mux
  Data_s1_address <= A_EXT (A_SRL(shifted_address_to_Data_s1_from_cpu_data_master,std_logic_vector'("00000000000000000000000000000010")), 2);
  --d1_Data_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_Data_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_Data_s1_end_xfer <= Data_s1_end_xfer;
      end if;
    end if;

  end process;

  --Data_s1_waits_for_read in a cycle, which is an e_mux
  Data_s1_waits_for_read <= Data_s1_in_a_read_cycle AND Data_s1_begins_xfer;
  --Data_s1_in_a_read_cycle assignment, which is an e_assign
  Data_s1_in_a_read_cycle <= internal_cpu_data_master_granted_Data_s1 AND cpu_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= Data_s1_in_a_read_cycle;