monitor.sts

Cadence16.2完全学习手册

#Allegro PCB Router v16-2-57 made 2008/10/14 at 13:29:47
#Host 
#ROUTING STATUS <<< F:/wenjian/第十一章/快速摆放元件\placed.dsn >>>
Start  Time: Report Time: Mon May 04 09:35:59 2009

Nets         =      182   Connections         =      572
Current Wire =       48   Reroute wires       =       48
Completion   =    2.80%   Unconnections       =      556
| ROUTING HISTORY ================================================================
|     Pass     |   Conflicts |    |     |     |     |    |Red|      CPU Time     |
|   Name   |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % |  Pass   |  Total  |
|----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
| Fanout   |  1|     0|     0|   0|  570|    2|    0|   0|   |  0:00:00|  0:00:00|
| Fanout   |  2|     0|     0|   0|  556|   50|    0|   0|   |  0:00:00|  0:00:00|
| Conflicts between polygon wires and fixed objects:   0