specctra.log,2

Cadence16.2完全学习手册

# 
# ===============================================================================
#                               Allegro PCB Router                               
# Copyright 1990-2006 Cadence Design Systems, Inc.  All Rights Reserved.
# ===============================================================================
# 
# Software licensed for sale by Cadence Design Systems, Inc.
# Current time = Mon May 04 11:00:02 2009
# 
# Allegro PCB Router v16-2-57 made 2008/10/14 at 13:29:47
# Running on: pc-20090426gjon, OS Version: WindowsNT 5.1.2600, Architecture: Intel Pentium
# Licensing: The program will not obey any unlicensed rules
# No graphics will be displayed.
# Design Name F:/wenjian/第十一章/自动布线\plane.dsn
# Batch File Name: pasde.do
# Did File Name: F:/wenjian/第十一章/自动布线/specctra.did
# Current time = Mon May 04 11:00:02 2009
# PCB F:/wenjian/第十一章/自动布线
# Master Unit set up as: MIL 1000
# PCB Limits xlo=-1192.5000 ylo=-590.0000 xhi=4142.5000 yhi=4470.0000
# Total 69 Images Consolidated.
# Via VIA z=1, 2 xlo=-12.0000 ylo=-12.0000 xhi= 12.0000 yhi= 12.0000
# 
#    VIA     TOP  BOTTOM
# 
#    TOP  ------   VIA  
# BOTTOM   VIA    ------
# 
# Wires Processed 0, Vias Processed 0
# Using colormap in design file.
# Layers Processed: Signal Layers 2
# Layers Processed: Power Layers 2
# Components Placed 85, Images Processed 100, Padstacks Processed 13
# Nets Processed 182, Net Terminals 772
# PCB Area=21340000.000  EIC=59  Area/EIC=361694.915  SMDs=65
# Total Pin Count: 839
# Signal Connections Created 431
# 
# Design Rules --------------------------------------------
# Via Grid 0.0100 with offset 0.0000
# Layer TOP Horz Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Layer BOTTOM Vert Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Cpu Time = 0:00:00  Elapsed Time = 0:00:00
# 
# Wiring Statistics ----------------- F:/wenjian/第十一章/自动布线\plane.dsn
# Nets 182 Connections 572 Unroutes 572
# Signal Layers 2 Power Layers 2
# Wire Junctions 0, at vias 0 Total Vias 0
# Percent Connected    0.00
# Manhattan Length 337942.0000 Horizontal 160801.1650 Vertical 177140.8350
# Routed Length   0.0000 Horizontal   0.0000 Vertical   0.0000
# Ratio Actual / Manhattan   0.0000
# Unconnected Length 337942.0000 Horizontal 150311.0000 Vertical 187631.0000
# Total Conflicts: 0 (Cross: 0, Clear: 0, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Cpu Time = 0:00:00  Elapsed Time = 0:00:01
# Loading Do File pasde.do ...
# Loading Do File F:/wenjian/第十一章/自动布线\plane_rules.do ...
# Nets VD0 and VD3 have been defined as a balanced pair.
# Nets RD3 and RD0 have been defined as a balanced pair.
# Nets RA3 and RA0 have been defined as a balanced pair.
# Nets BD0 and BD3 have been defined as a balanced pair.
# Nets N16740 and N16748 have been defined as a balanced pair.
# Nets BA0 and BA3 have been defined as a balanced pair.
# Nets D10 and D13 have been defined as a balanced pair.
# Nets A20 and A23 have been defined as a balanced pair.
# Nets A10 and A13 have been defined as a balanced pair.
# <<WARNING:>> Could not form pair of nets RCS3 and RCS0.
# <<WARNING:>> Could not form pair of nets Q3 and Q0.
# Nets D0 and D3 have been defined as a balanced pair.
# Nets RA13 and RA10 have been defined as a balanced pair.
# Nets A0 and A3 have been defined as a balanced pair.
# Nets BD10 and BD13 have been defined as a balanced pair.
# Colormap Written to File _notify.std
# Enter command <# Loading Do File C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaal03820.tmp ...
# All Components Unselected.
# All Nets Unselected.
# Net VCC Selected.
# Net GND Selected.
# Net RA14 Selected.
# Net RA10 Selected.
# Net RA13 Selected.
# Net RD1 Selected.
# Net DCLK Selected.
# Net RA12 Selected.
# Net RD4 Selected.
# Net RA13 Selected.
# Net RA10 Selected.
# Net RA4 Selected.
# Net RA15 Selected.
# Net RD7 Selected.
# Net RD0 Selected.
# Net RD3 Selected.
# Net RA8 Selected.
# Net RD3 Selected.
# Net RD0 Selected.
# Net RA5 Selected.
# Net N17076 Selected.
# Net RD6 Selected.
# Net A23 Selected.
# Net A20 Selected.
# Net RA9 Selected.
# Net A22 Selected.
# Net RA11 Selected.
# Net A21 Selected.
# Net N17072 Selected.
# Net RA1 Selected.
# Net A20 Selected.
# Net A23 Selected.
# Net N16756 Selected.
# Net RA0 Selected.
# Net RA3 Selected.
# Net A19 Selected.
# Net BNC3 Selected.
# Net A18 Selected.
# Net GND_EARTH Selected.
# Net A17 Selected.
# Net BNC2 Selected.
# Net A16 Selected.
# Net N17068 Selected.
# Net RCS1 Selected.
# Net A15 Selected.
# Net OUTA Selected.
# Net A14 Selected.
# Net N16748 Selected.
# Net N16740 Selected.
# Net WSTAT Selected.
# Net A13 Selected.
# Net A10 Selected.
# Net N17064 Selected.
# Net VCLKA Selected.
# Net A12 Selected.
# Net N17060 Selected.
# Net RCS0 Selected.
# Net A11 Selected.
# Net RCS2 Selected.
# Net A10 Selected.
# Net A13 Selected.
# Net RCS3 Selected.
# Net A9 Selected.
# Net N17056 Selected.
# Net NCS Selected.
# Net A8 Selected.
# Net N16740 Selected.
# Net N16748 Selected.
# Net GAIN Selected.
# Net A7 Selected.
# Net OUTB Selected.
# Net A6 Selected.
# Net RWE Selected.
# Net A5 Selected.
# Net OE Selected.
# Net A4 Selected.
# Net Q2 Selected.
# Net A3 Selected.
# Net A0 Selected.
# Net VCLKC Selected.
# Net Q7 Selected.
# Net A2 Selected.
# Net DATA Selected.
# Net Q6 Selected.
# Net A1 Selected.
# Net Q4 Selected.
# Net A0 Selected.
# Net A3 Selected.
# Net Q5 Selected.
# Net Q0 Selected.
# Net Q1 Selected.
# Net Q3 Selected.
# Net D8 Selected.
# Net V12P Selected.
# Net AGND Selected.
# Net D12 Selected.
# Net V12N Selected.
# Net BA7 Selected.
# Net D11 Selected.
# Net BA6 Selected.
# Net D1 Selected.
# Net BA5 Selected.
# Net BA4 Selected.
# Net BA3 Selected.
# Net BA0 Selected.
# Net D13 Selected.
# Net D10 Selected.
# Net BA2 Selected.
# Net D14 Selected.
# Net BA1 Selected.
# Net D15 Selected.
# Net BA0 Selected.
# Net BA3 Selected.
# Net D3 Selected.
# Net D0 Selected.
# Net BD15 Selected.
# Net D4 Selected.
# Net BD14 Selected.
# Net D2 Selected.
# Net BD13 Selected.
# Net BD10 Selected.
# Net D5 Selected.
# Net BD12 Selected.
# Net D9 Selected.
# Net BD11 Selected.
# Net BD10 Selected.
# Net BD13 Selected.
# Net D10 Selected.
# Net D13 Selected.
# Net BD9 Selected.
# Net BD8 Selected.
# Net D0 Selected.
# Net D3 Selected.
# Net BD7 Selected.
# Net D6 Selected.
# Net BD6 Selected.
# Net D7 Selected.
# Net BD5 Selected.
# Net BD4 Selected.
# Net N17361 Selected.
# Net BD3 Selected.
# Net BD0 Selected.
# Net BD2 Selected.
# Net N17197 Selected.
# Net BD1 Selected.
# Net N17221 Selected.
# Net BD0 Selected.
# Net BD3 Selected.
# Net N17281 Selected.
# Net N17269 Selected.
# Net N17341 Selected.
# Net DHEN Selected.
# Net DEN Selected.
# Net MWR Selected.
# Net MRD Selected.
# Net RDY Selected.
# Net DDIR Selected.
# Net AEN Selected.
# Net WAIT Selected.
# Net N17361_4621 Selected.
# Net MCLK Selected.
# Net N17197_4623 Selected.
# Net RESET Selected.
# Net N17221_4624 Selected.
# Net BWR Selected.
# Net BRESET Selected.
# Net N17281_4627 Selected.
# Net BRD Selected.
# Net SEL Selected.
# Net N17269_4629 Selected.
# Net FPGA Selected.
# Net HS Selected.
# Net N17341_4632 Selected.
# Net N30149 Selected.
# Net N30003 Selected.
# Net VREF Selected.
# Net N29863 Selected.
# Net N29715 Selected.
# Net VD7 Selected.
# Net VD6 Selected.
# Net VD5 Selected.
# Net VD4 Selected.
# Net VD3 Selected.
# Net VD0 Selected.
# Net VD2 Selected.
# Net VD1 Selected.
# Net VD0 Selected.
# Net VD3 Selected.
# Net N407439 Selected.
# Net N17052 Selected.
# Net N16732 Selected.
# Net N17048 Selected.
# Net N17044 Selected.
# Net GND_POWER Selected.
# Net N17104 Selected.
# Net N17100 Selected.
# Net N17096 Selected.
# Net N17092 Selected.
# Net RA3 Selected.
# Net RA0 Selected.
# Net RA2 Selected.
# Net RD2 Selected.
# Net N17088 Selected.
# Net RA7 Selected.
# Net N17084 Selected.
# Net RD5 Selected.
# Net N17080 Selected.
# Net RA6 Selected.
set route_diagonal 4
grid wire 0.010000 (direction x) (offset 0.000000)
grid wire 0.010000 (direction y) (offset 0.000000)
grid via 0.010000 (direction x) (offset 0.000000)
grid via 0.010000 (direction y) (offset 0.000000)
protect all wires
# All Wires Protected.
direction TOP horizontal
select layer TOP
unprotect layer_wires TOP
# Wires on layer TOP were Unprotected.
direction BOTTOM vertical
select layer BOTTOM
unprotect layer_wires BOTTOM
# Wires on layer BOTTOM were Unprotected.
cost via 100
set turbo_stagger on
limit outside 32.000000
rule pcb (patterns_allowed  trombone accordion)
set pattern_stacking on
rule pcb (sawtooth_amplitude -1 -1)
rule pcb (sawtooth_gap -1)
rule pcb (accordion_amplitude -1 -1)
rule pcb (accordion_gap -1)
rule pcb (trombone_run_length -1)
rule pcb (trombone_gap -1)
route 25 1
# Current time = Mon May 04 11:01:52 2009
# 
#    VIA     TOP  BOTTOM
# 
#    TOP  ------   VIA  
# BOTTOM   VIA    ------
# 
# 
# Design Rules --------------------------------------------
# Via Grid 0.0100 with offset 0.0000
# Layer TOP Horz Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Layer BOTTOM Vert Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# 
# Wiring Statistics ----------------- F:/wenjian/第十一章/自动布线\plane.dsn
# Nets 182 Connections 572 Unroutes 572
# Signal Layers 2 Power Layers 2
# Wire Junctions 0, at vias 0 Total Vias 0
# Percent Connected    0.00
# Manhattan Length 338257.0000 Horizontal 160989.9200 Vertical 177267.0800
# Routed Length   0.0000 Horizontal   0.0000 Vertical   0.0000
# Ratio Actual / Manhattan   0.0000
# Unconnected Length 338257.0000 Horizontal 149956.0000 Vertical 188301.0000
# 0 bend points have been removed.
# 0 bend points have been removed.
# 0 bend points have been removed.
# Start Route Pass 1 of 25
# Routing 572 wires.
# 56 bend points have been removed.
# 28 bend points have been removed.
# Total Conflicts: 897 (Cross: 787, Clear: 110, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 249
# Attempts 535 Successes 294 Failures 241 Vias 4
# Cpu Time = 0:00:03  Elapsed Time = 0:00:02
# End Pass 1 of 25