allegro.jrl,1

Cadence16.2完全学习手册

\i (00:24:37) setwindow pcb
\i (00:24:37) zoom in 2102.22 947.45
\i (00:24:37) trapsize 3042
\i (00:24:37) zoom in 1 
\i (00:24:37) setwindow pcb
\i (00:24:37) zoom in 2102.22 947.45
\i (00:24:37) trapsize 1521
\i (00:24:38) zoom out 1 
\i (00:24:38) setwindow pcb
\i (00:24:38) zoom out 2698.46 1041.76
\i (00:24:38) trapsize 3042
\i (00:24:39) zoom out 1 
\i (00:24:39) setwindow pcb
\i (00:24:39) zoom out 2698.47 1041.76
\i (00:24:39) trapsize 6084
\i (00:24:43) pick grid 3303.09 5227.59
\t (00:24:43) last pick:  3300.00  5225.00
\i (00:24:43) pick grid 1161.50 3268.52
\t (00:24:43) last pick:  1150.00  3275.00
\i (00:24:44) drag_start grid 1344.02 3292.85
\i (00:24:44) drag_stop 1331.85 3718.74
\i (00:24:45) pick grid 1283.18 3317.19
\t (00:24:45) last pick:  1275.00  3325.00
\i (00:24:46) pick grid 978.98 3584.89
\t (00:24:46) last pick:  975.00  3575.00
\i (00:24:46) pick grid 1149.33 3633.56
\t (00:24:46) last pick:  1150.00  3625.00
\i (00:24:48) move 
\t (00:24:48) Cannot edit Connect Pin "U6.84". Symbol or drawing must have UNFIXED_PINS property.
\t (00:24:48) No valid items selected for the current operation, exiting.
\i (00:24:48) generaledit 
\i (00:24:50) drag_start grid 1051.99 3597.06
\i (00:24:50) move 
\t (00:24:50) last pick:  1100.00  3050.00
\t (00:24:50) Moving U6 / EPF8282A/LCC / PLCC84.
\t (00:24:50) Pick new location for the element(s).
\i (00:24:54) drag_stop grid 1051.99 3061.66
\i (00:24:54) generaledit 
\i (00:24:55) pick grid 1051.99 3061.66
\t (00:24:55) last pick:  1050.00  3050.00
\i (00:24:57) pick grid 954.64 1382.46
\t (00:24:57) last pick:  950.00  1375.00
\i (00:24:58) drag_start grid 1027.65 1589.32
\i (00:24:58) move 
\t (00:24:58) last pick:  1050.00  850.00
\t (00:24:58) Moving U4 / 20L10 / DIP24.
\t (00:24:58) Pick new location for the element(s).
\i (00:25:02) drag_stop grid 1064.16 859.23
\i (00:25:02) generaledit 
\i (00:25:05) zoom out 1 
\i (00:25:05) setwindow pcb
\i (00:25:05) zoom out 1721.23 2818.30
\i (00:25:05) trapsize 12168
\i (00:25:05) zoom out 1 
\i (00:25:05) setwindow pcb
\i (00:25:05) zoom out 6515.48 2647.94
\i (00:25:05) trapsize 19187
\i (00:25:06) zoom in 1 
\i (00:25:06) setwindow pcb
\i (00:25:06) zoom in 2334.09 2563.21
\i (00:25:06) trapsize 9594
\i (00:25:06) zoom in 1 
\i (00:25:06) setwindow pcb
\i (00:25:06) zoom in 2410.84 2601.59
\i (00:25:06) trapsize 4797
\i (00:25:07) zoom in 1 
\i (00:25:07) setwindow pcb
\i (00:25:07) zoom in 1777.66 2879.81
\i (00:25:07) trapsize 2398
\i (00:25:07) zoom in 1 
\i (00:25:07) setwindow pcb
\i (00:25:07) zoom in 2156.62 2899.00
\i (00:25:07) trapsize 1199
\i (00:25:09) zoom out 1 
\i (00:25:09) setwindow pcb
\i (00:25:09) zoom out 2302.93 2903.80
\i (00:25:09) trapsize 2398
\i (00:25:13) zoom out 1 
\i (00:25:13) setwindow pcb
\i (00:25:13) zoom out 2302.92 2865.43
\i (00:25:13) trapsize 4797
\i (00:25:16) color192 
\i (00:25:16) setwindow cvf.dialog
\i (00:25:16) cvf layer_mode
\i (00:25:16) setwindow pcb
\i (00:25:16) generaledit 
\i (00:25:17) setwindow cvf.dialog
\i (00:25:17) cvf layer_tree_item 'Display'
\i (00:25:19) cvf bkgrnd_clr 50331647
\i (00:25:23) cvf customize 1 33554432
\i (00:25:24) cvf bkgrnd_clr 33554432
\i (00:25:28) cvf apply
\i (00:25:34) cvf layer_tree_item 'Conductor' 'Stack-Up'
\i (00:25:38) cvf select_color_cell 23
\i (00:25:40) cvf layers_color stack-up pin/gnd 24
\i (00:25:40) cvf layers_color stack-up via/gnd 24
\i (00:25:41) cvf layers_color stack-up etch/gnd 24
\i (00:25:42) cvf apply
\i (00:25:49) setwindow pcb
\i (00:25:49) zoom out 1 
\i (00:25:49) setwindow pcb
\i (00:25:49) zoom out 5574.37 3057.30
\i (00:25:49) trapsize 9594
\i (00:25:49) zoom out 1 
\i (00:25:49) setwindow pcb
\i (00:25:49) zoom out 7648.99 2922.99
\i (00:25:49) trapsize 19187
\i (00:25:50) zoom in 1 
\i (00:25:50) setwindow pcb
\i (00:25:50) zoom in -313.77 1642.21
\i (00:25:50) trapsize 9594
\i (00:25:50) zoom in 1 
\i (00:25:50) setwindow pcb
\i (00:25:50) zoom in 223.48 1661.40
\i (00:25:50) trapsize 4797
\i (00:25:51) zoom out 1 
\i (00:25:51) setwindow pcb
\i (00:25:51) zoom out 357.79 1690.19
\i (00:25:51) trapsize 9594
\i (00:25:51) zoom out 1 
\i (00:25:51) setwindow pcb
\i (00:25:51) zoom out 357.79 1690.19
\i (00:25:51) trapsize 19187
\i (00:25:54) open 
\f (00:25:54) Do you want to save the changes you made to demo_placed.brd?
\i (00:25:56) fillin no 
\i (00:26:01) fillin "F:\Cadence 例子\Candence 16.2\demo_placed.brd"
\i (00:26:01) cd "F:\Cadence 例子\Candence 16.2"
\i (00:26:01) setwindow cvf.dialog
\i (00:26:01) cvf form_close
\t (00:26:01) Opening existing drawing...
\w (00:26:01) WARNING(SPMHDB-214): Allegro PCB Design GXL opening an Allegro Expert design.
\w (00:26:01) WARNING(SPMHDB-213): DRC set to "out of date". This product supports a different DRC set than last product used on drawing.
\w (00:26:01) WARNING(SPMHOD-34): Database was last saved by lower tier tool ... Allegro Expert. DRC is set out-of-date so you may wish to update DRC to insure design rules are being followed.
\i (00:26:02) fillin confirm
\i (00:26:02) setwindow pcb
\i (00:26:02) trapsize 6672
\d (00:26:03) Database opened: F:/Cadence 例子/Candence 16.2/demo_placed.brd
\i (00:26:03) generaledit 
\i (00:26:07) color192 
\i (00:26:07) setwindow cvf.dialog
\i (00:26:07) cvf layer_mode
\i (00:26:07) setwindow pcb
\i (00:26:07) generaledit 
\i (00:26:09) setwindow cvf.dialog
\i (00:26:09) cvf layer_tree_item 'Display'
\i (00:26:20) cvf customize 1 33554432
\i (00:26:22) cvf bkgrnd_clr 33554432
\i (00:26:26) cvf apply
\i (00:26:31) setwindow pcb
\i (00:26:31) pick grid 2379.34 4940.78
\t (00:26:31) last pick:  2375.00  4950.00
\i (00:26:31) zoom in 1 
\i (00:26:31) setwindow pcb
\i (00:26:31) zoom in 2352.65 4540.45
\i (00:26:31) trapsize 3336
\i (00:26:31) zoom in 1 
\i (00:26:31) setwindow pcb
\i (00:26:31) zoom in 2352.65 4540.45
\i (00:26:31) trapsize 1668
\i (00:26:32) zoom out 1 
\i (00:26:32) setwindow pcb
\i (00:26:32) zoom out 2352.65 4540.46
\i (00:26:32) trapsize 3336
\i (00:26:32) zoom out 1 
\i (00:26:32) setwindow pcb
\i (00:26:32) zoom out 2352.65 4540.46
\i (00:26:32) trapsize 6672
\i (00:26:32) zoom out 1 
\i (00:26:32) setwindow pcb
\i (00:26:32) zoom out 2352.65 4487.09
\i (00:26:32) trapsize 13344
\i (00:26:33) zoom in 1 
\i (00:26:33) setwindow pcb
\i (00:26:33) zoom in 2204.28 1811.03
\i (00:26:33) trapsize 6672
\i (00:26:33) zoom in 1 
\i (00:26:33) setwindow pcb
\i (00:26:33) zoom in 2164.25 1677.59
\i (00:26:33) trapsize 3336
\i (00:26:34) zoom out 1 
\i (00:26:34) setwindow pcb
\i (00:26:34) zoom out 2157.58 1670.92
\i (00:26:34) trapsize 6672
\i (00:26:34) zoom out 1 
\i (00:26:34) setwindow pcb
\i (00:26:34) zoom out 2197.62 1630.90
\i (00:26:34) trapsize 13344
\i (00:26:40) setwindow cvf.dialog
\i (00:26:40) cvf select_color_cell 1
\i (00:26:41) cvf ratsbb_clr 1
\i (00:26:42) cvf apply
\i (00:26:46) setwindow pcb
\i (00:26:46) pick grid 2544.56 1577.52
\t (00:26:46) last pick:  2550.00  1575.00
\i (00:26:47) zoom in 1 
\i (00:26:47) setwindow pcb
\i (00:26:47) zoom in 2517.87 1604.21
\i (00:26:47) trapsize 6672
\i (00:26:47) zoom in 1 
\i (00:26:47) setwindow pcb
\i (00:26:47) zoom in 2517.88 1604.21
\i (00:26:47) trapsize 3336
\i (00:26:47) zoom out 1 
\i (00:26:47) setwindow pcb
\i (00:26:47) zoom out 2517.88 1604.22
\i (00:26:47) trapsize 6672
\i (00:26:48) zoom out 1 
\i (00:26:48) setwindow pcb
\i (00:26:48) zoom out 2517.89 1604.21
\i (00:26:48) trapsize 13344
\i (00:26:54) setwindow cvf.dialog
\i (00:26:54) cvf grids_clr 1
\i (00:26:55) cvf select_color_cell 23
\i (00:26:57) cvf grids_clr 23
\i (00:26:59) cvf apply
\i (00:27:04) cvf layer_tree_item 'Stack-Up'
\i (00:27:16) cvf select_color_cell 3
\i (00:27:17) cvf layers_color stack-up pin/top 4
\i (00:27:18) cvf layers_color stack-up via/top 4
\i (00:27:18) cvf layers_color stack-up etch/top 4
\i (00:27:20) cvf apply
\i (00:27:23) setwindow pcb
\i (00:27:23) zoom in 1 
\i (00:27:23) setwindow pcb
\i (00:27:23) zoom in 2704.71 1497.46
\i (00:27:23) trapsize 6672
\i (00:27:23) zoom in 1 
\i (00:27:23) setwindow pcb
\i (00:27:23) zoom in 2704.71 1497.47
\i (00:27:23) trapsize 3336
\i (00:27:24) zoom out 1 
\i (00:27:24) setwindow pcb
\i (00:27:24) zoom out 2711.38 1470.78
\i (00:27:24) trapsize 6672
\i (00:27:25) zoom out 1 
\i (00:27:25) setwindow pcb
\i (00:27:25) zoom out 2884.86 1404.06
\i (00:27:25) trapsize 13344
\i (00:27:32) setwindow cvf.dialog
\i (00:27:32) cvf select_color_cell 7
\i (00:27:33) cvf layers_color stack-up pin/bottom 8
\i (00:27:34) cvf layers_color stack-up via/bottom 8
\i (00:27:34) cvf layers_color stack-up etch/bottom 8
\i (00:27:36) cvf apply
\i (00:27:38) setwindow pcb
\i (00:27:38) pick grid 5620.42 4206.36
\t (00:27:38) last pick:  5625.00  4200.00
\i (00:27:38) zoom in 1 
\i (00:27:38) setwindow pcb
\i (00:27:38) zoom in 1830.64 1137.17
\i (00:27:38) trapsize 6672
\i (00:27:38) zoom in 1 
\i (00:27:38) setwindow pcb
\i (00:27:38) zoom in 1830.64 1137.17
\i (00:27:38) trapsize 3336
\i (00:27:39) zoom in 1 
\i (00:27:39) setwindow pcb
\i (00:27:39) zoom in 1830.64 1137.18
\i (00:27:39) trapsize 1668
\i (00:27:39) zoom out 1 
\i (00:27:39) setwindow pcb
\i (00:27:39) zoom out 1830.64 1137.18
\i (00:27:39) trapsize 3336
\i (00:27:39) zoom out 1 
\i (00:27:39) setwindow pcb
\i (00:27:39) zoom out 1830.64 1137.18
\i (00:27:39) trapsize 6672
\i (00:27:40) zoom out 1 
\i (00:27:40) setwindow pcb
\i (00:27:40) zoom out 1830.64 1137.17
\i (00:27:40) trapsize 13344
\i (00:27:50) pick grid 1857.33 1857.77
\t (00:27:50) last pick:  1850.00  1850.00
\i (00:27:50) zoom in 1 
\i (00:27:50) setwindow pcb
\i (00:27:50) zoom in 1857.33 1857.77
\i (00:27:50) trapsize 6672
\i (00:27:50) zoom in 1 
\i (00:27:50) setwindow pcb
\i (00:27:50) zoom in 1857.33 1857.77
\i (00:27:50) trapsize 3336
\i (00:27:52) zoom out 1 
\i (00:27:52) setwindow pcb
\i (00:27:52) zoom out 1857.33 1851.10
\i (00:27:52) trapsize 6672
\i (00:27:52) zoom out 1 
\i (00:27:52) setwindow pcb
\i (00:27:52) zoom out 1857.33 1851.11
\i (00:27:52) trapsize 13344
\i (00:27:59) pick grid 1003.30 -2872.78
\t (00:27:59) last pick:  1000.00  -2875.00
\i (00:27:59) pick grid 309.40 -2178.88
\t (00:27:59) last pick:  300.00  -2175.00
\i (00:28:00) zoom in 1 
\i (00:28:00) setwindow pcb
\i (00:28:00) zoom in -864.90 3692.62
\i (00:28:00) trapsize 6672
\i (00:28:00) zoom in 1 
\i (00:28:00) setwindow pcb
\i (00:28:00) zoom in -838.21 3919.48
\i (00:28:00) trapsize 3336
\i (00:28:01) zoom in 1 
\i (00:28:01) setwindow pcb
\i (00:28:01) zoom in -838.20 3452.43
\i (00:28:01) trapsize 1668
\i (00:28:01) zoom in 1 
\i (00:28:01) setwindow pcb
\i (00:28:01) zoom in -838.20 3452.43
\i (00:28:01) trapsize 834
\i (00:28:02) zoom out 1 
\i (00:28:02) setwindow pcb
\i (00:28:02) zoom out -824.86 3399.05
\i (00:28:02) trapsize 1668
\i (00:28:03) zoom out 1 
\i (00:28:03) setwindow pcb
\i (00:28:03) zoom out -824.85 3399.06
\i (00:28:03) trapsize 3336
\i (00:28:03) zoom out 1 
\i (00:28:03) setwindow pcb
\i (00:28:03) zoom out -824.86 3399.06
\i (00:28:03) trapsize 6672
\i (00:28:03) zoom out 1 
\i (00:28:03) setwindow pcb
\i (00:28:03) zoom out -824.85 3399.06
\i (00:28:03) trapsize 13344
\i (00:28:03) zoom out 1 
\i (00:28:03) setwindow pcb
\i (00:28:03) zoom out -544.65 3692.63
\i (00:28:03) trapsize 19187
\i (00:28:09) setwindow cvf.dialog
\i (00:28:09) cvf layers_visible stack-up etch/all_row TRUE
\i (00:28:10) cvf layers_visible stack-up drc/all_row TRUE
\i (00:28:11) cvf layers_visible stack-up flow_plan/all_row TRUE
\i (00:28:12) cvf layers_visible stack-up anti_etch/all_row TRUE
\i (00:28:14) cvf layers_visible stack-up boundary/all_row TRUE
\i (00:28:15) cvf layers_visible stack-up pin/all_row TRUE
\i (00:28:17) cvf layers_visible stack-