sxx.opj

来自「Cadence16.2完全学习手册」· OPJ 代码 · 共 95 行

(ExpressProject "sxx"
  (ProjectVersion "19981106")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
    (File ".\sxx.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (DRC_Scope "0")
    (DRC_Action "0")
    (DRC_Create_Warnings "FALSE")
    (DRC_Check_Ports "FALSE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    (DRC_Check_for_Misleading_TAP "FALSE")
    (DRC_Visible_Power_pins "FALSE")
    (DRC_Report_Netnames "FALSE")
    (DRC_View_Output "FALSE")
    (DRC_Report_File "E:\CADENCE\SXX.DRC")
    (ANNOTATE_Scope "0")
    (ANNOTATE_Mode "1")
    (ANNOTATE_Action "0")
    (Annotate_Page_Order "0")
    (ANNOTATE_Reset_References_to_1 "FALSE")
    (ANNOTATE_No_Page_Number_Change "FALSE")
    (ANNOTATE_Property_Combine "{Value}{Source Package}{POWER_GROUP}")
    (ANNOTATE_IncludeNonPrimitive "FALSE")
    (ANNOTATE_Refdes_Control_Required "FALSE")
    (Annotate_type "Default")
    (width_pages "100")
    (width_start "80")
    (width_End "80")
    (FLDSTUFF_Scope "0")
    (FLDSTUFF_Action "0")
    (FLDSTUFF_Report_File "E:\Cadence\sxx.RPT")
    (FLDSTUFF_Update_File "E:\Cadence\sxx.UPD")
    (FLDSTUFF__Uppercase_Result_Property "FALSE")
    (FLDSTUFF_Uppercase_Update_Property "FALSE")
    (FLDSTUFF_Uppercase_Unconditionally "FALSE")
    (FLDSTUFF_Visibility "0")
    (FLDSTUFF_inst_or_occurrence "0")
    (FLDSTUFF_Create_Report_File "FALSE")
    (Netlist_TAB "0"))
  (Folder "Outputs"
    (File ".\sxx.drc"
      (Type "Report"))
    (File ".\allegro\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\allegro\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File ".\allegro\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat")))
  (Folder "Referenced Projects")
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources"
         "E:\Cadence001\wenjian\第五章\从原理图到PCB图的实现  5.5\sxx.dsn")
      (Path "Design Resources"
         "E:\Cadence001\wenjian\第五章\从原理图到PCB图的实现  5.5\sxx.dsn"
         "SCHEMATIC1")
      (Path "Outputs")
      (Select "Design Resources"
         "E:\Cadence001\wenjian\第五章\从原理图到PCB图的实现  5.5\sxx.dsn"
         "SCHEMATIC1" "PAGE1"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 0 1 -1 -1 -4 -30 0 200 0 267"))
      (Tab 0))
    (Doc
      (Type "COrSchematicDoc")
      (Frame
        (Placement "44 0 1 -1 -1 -4 -30 66 914 87 388")
        (Scroll "0 0")
        (Zoom "100")
        (Occurrence "/"))
      (Path "E:\CADENCE001\WENJIAN\第五章\从原理图到PCB图的实现  5.5\SXX.DSN")
      (Schematic "SCHEMATIC1")
      (Page "PAGE1")))
  (MPSSessionName "Administrator")
  (PartMRUSelector)
  (ISPCBBASICLICENSE "false"))