_primary.vhd

来自「对串行输入的数据流进行检测的ＶＥＲＩＬＯＧ源代码」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity seqdet is
    generic(
        IDLE            : integer := 0;
        A               : integer := 1;
        B               : integer := 2;
        C               : integer := 3;
        D               : integer := 4;
        E               : integer := 5;
        F               : integer := 6;
        G               : integer := 7
    );
    port(
        x               : in     vl_logic;
        z               : out    vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end seqdet;