moore.tan.rpt

moore状态机用VHDL语言进行实现

; N/A   ; None         ; 2.104 ns   ; read_write ; present_state.write    ; clk      ;
; N/A   ; None         ; 1.977 ns   ; ready      ; present_state.write    ; clk      ;
; N/A   ; None         ; 1.976 ns   ; ready      ; present_state.decision ; clk      ;
; N/A   ; None         ; 1.974 ns   ; ready      ; present_state.idle     ; clk      ;
; N/A   ; None         ; 1.961 ns   ; ready      ; present_state.read     ; clk      ;
; N/A   ; None         ; 1.858 ns   ; read_write ; present_state.read     ; clk      ;
+-------+--------------+------------+------------+------------------------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+---------------------+----+------------+
; Slack ; Required tco ; Actual tco ; From                ; To ; From Clock ;
+-------+--------------+------------+---------------------+----+------------+
; N/A   ; None         ; 9.898 ns   ; present_state.write ; we ; clk        ;
; N/A   ; None         ; 9.579 ns   ; present_state.idle  ; we ; clk        ;
; N/A   ; None         ; 9.531 ns   ; present_state.idle  ; oe ; clk        ;
; N/A   ; None         ; 8.976 ns   ; present_state.read  ; oe ; clk        ;
+-------+--------------+------------+---------------------+----+------------+


+------------------------------------------------------------------------------------------+
; th                                                                                       ;
+---------------+-------------+-----------+------------+------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To                     ; To Clock ;
+---------------+-------------+-----------+------------+------------------------+----------+
; N/A           ; None        ; -1.304 ns ; read_write ; present_state.read     ; clk      ;
; N/A           ; None        ; -1.407 ns ; ready      ; present_state.read     ; clk      ;
; N/A           ; None        ; -1.420 ns ; ready      ; present_state.idle     ; clk      ;
; N/A           ; None        ; -1.422 ns ; ready      ; present_state.decision ; clk      ;
; N/A           ; None        ; -1.423 ns ; ready      ; present_state.write    ; clk      ;
; N/A           ; None        ; -1.550 ns ; read_write ; present_state.write    ; clk      ;
+---------------+-------------+-----------+------------+------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 06 17:03:04 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off moore -c moore
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 304.04 MHz between source register "present_state.write" and destination register "present_state.idle"
    Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.102 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y2_N5; Fanout = 3; REG Node = 'present_state.write'
            Info: 2: + IC(0.919 ns) + CELL(1.183 ns) = 2.102 ns; Loc. = LC_X4_Y2_N9; Fanout = 4; REG Node = 'present_state.idle'
            Info: Total cell delay = 1.183 ns ( 56.28 % )
            Info: Total interconnect delay = 0.919 ns ( 43.72 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y2_N9; Fanout = 4; REG Node = 'present_state.idle'
                Info: Total cell delay = 2.081 ns ( 62.16 % )
                Info: Total interconnect delay = 1.267 ns ( 37.84 % )
            Info: - Longest clock path from clock "clk" to source register is 3.348 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y2_N5; Fanout = 3; REG Node = 'present_state.write'
                Info: Total cell delay = 2.081 ns ( 62.16 % )
                Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: + Micro clock to output delay of source is 0.376 ns
        Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "present_state.write" (data pin = "read_write", clock pin = "clk") is 2.104 ns
    Info: + Longest pin to register delay is 5.119 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_15; Fanout = 2; PIN Node = 'read_write'
        Info: 2: + IC(2.926 ns) + CELL(1.061 ns) = 5.119 ns; Loc. = LC_X4_Y2_N5; Fanout = 3; REG Node = 'present_state.write'
        Info: Total cell delay = 2.193 ns ( 42.84 % )
        Info: Total interconnect delay = 2.926 ns ( 57.16 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y2_N5; Fanout = 3; REG Node = 'present_state.write'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
Info: tco from clock "clk" to destination pin "we" through register "present_state.write" is 9.898 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y2_N5; Fanout = 3; REG Node = 'present_state.write'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 6.174 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y2_N5; Fanout = 3; REG Node = 'present_state.write'
        Info: 2: + IC(0.982 ns) + CELL(0.511 ns) = 1.493 ns; Loc. = LC_X4_Y2_N6; Fanout = 1; COMB Node = 'we~0'
        Info: 3: + IC(2.359 ns) + CELL(2.322 ns) = 6.174 ns; Loc. = PIN_82; Fanout = 0; PIN Node = 'we'
        Info: Total cell delay = 2.833 ns ( 45.89 % )
        Info: Total interconnect delay = 3.341 ns ( 54.11 % )
Info: th for register "present_state.read" (data pin = "read_write", clock pin = "clk") is -1.304 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y2_N2; Fanout = 3; REG Node = 'present_state.read'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 4.873 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_15; Fanout = 2; PIN Node = 'read_write'
        Info: 2: + IC(2.558 ns) + CELL(1.183 ns) = 4.873 ns; Loc. = LC_X4_Y2_N2; Fanout = 3; REG Node = 'present_state.read'
        Info: Total cell delay = 2.315 ns ( 47.51 % )
        Info: Total interconnect delay = 2.558 ns ( 52.49 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 120 megabytes
    Info: Processing ended: Thu Nov 06 17:03:06 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01