wiredelay.sp

分析集成电路中线间电容的一个小例子

wire delay model
.opt list acct limpts=1000

.global vd
Vdd vd 0 5


.subckt inverter1 in out
Mp out in vd vd MOD2 W=96u L=0.8u
Mn out in 0   0   MOD1 W=32u L=0.8u
.ends inverter1

.subckt inverter2 in out
Mp out in vd vd MOD2 W=96u L=0.8u
Mn out in 0   0   MOD1 W=32u L=0.8u
.ends inverter2

.subckt buffer in out
Xint1 in 1 inverter1
Xint2 1 out inverter2
.ends buffer

.MODEL  MOD1  NMOS  VTO=1.0  KP=4.5E-5  LAMBDA=0  GAMMA=0.4
+TOX=1.0E-7  NSUB=4.0E+15  LD=0.06U  CJ=2.0E-4  MJ=0.5  
+CJSW=2.0E-10  MJSW=0.4	CGSO=1E-10	CGDO=1E-10	  CGBO=2E-9
.MODEL  MOD2  PMOS  VTO=-1.2  KP=2.5E-5  LAMBDA=0  GAMMA=0.4
+TOX=1.0E-7  NSUB=4.0E+15  LD=0.06U  CJ=2.0E-4  MJ=0.5  
+CJSW=2.0E-10  MJSW=0.4	CGSO=1E-10	CGDO=1E-10	  CGBO=2E-9

Xbuffer1 1  2  buffer
R  2  12  700
C1 3  0   155f
C2 12 0   155f

Vx 1 0 pulse( 0 5 0 0 0 10NS 20NS )

.TRAN 0.01NS 100NS
.meas tran delay1 trig V(1) val=2.5 rise=1
+                 targ V(12) val=2.5 rise=1
.meas tran delay2 trig V(1) val=2.5 rise=2
+                 targ V(12) val=2.5 rise=2
.PROBE
.END