wiredelay.lis

分析集成电路中线间电容的一个小例子

   4*** gate capacitance parameters ***
    capop=   2.00               cf1=   0.    volts        cf2= 100.00m volts  
      cf3=   1.00  volts        cf4=  50.00               cf5= 666.67m        
      cf6= 500.00               xqc= 500.00m              tox= 100.00n meters 
      cox= 345.31u f/m**2 

   5*** diffusion parasitic parameters ***
      acm=   0.                  is=  10.00f amps          js=   0.    a/m**2 
      jsw=   0.    amp/m        nds=   1.00               cbd=   0.    farad  
      cbs=   0.    farad         cj= 200.00u f/m**2      cjsw= 200.00p f/m    
   cjgate= 200.00p f/m           mj= 500.00m             mjsw= 400.00m        
       pb= 800.00m volts        php= 800.00m volts         tt=   0.    secs   
     hdif=   0.    meters      ldif=   0.    meters        rd=   0.    ohms   
       rs=   0.    ohms         rsh=   0.    ohms/sq       fc=   0.           
    alpha=   0.                 vcr=   0.    volts      iirat=   0.           
      rdc=   0.    ohms         rsc=   0.    ohms           n=   1.00         
     vnds=  -1.00  volts  

   6*** temperature effect parameters ***
     tlev=   0.               tlevc=   0.                  eg=   1.11  ev     
     gap1= 702.00u ev/deg      gap2=   1.11k deg          xti=   0.           
      bex=  -1.50               tcv=   0.    v/deg k      trd=   0.    /deg   
      trs=   0.    /deg         cta=   0.    /deg         ctp=   0.    /deg   

   7*** noise parameters ***
       kf=   0.                  af=   1.00              nlev=   2.00         
   gdsnoi=   1.00         

   ***  level  1  model parameters  ***

   lambda=   0.    /v            kp=  25.00u a/v**2 

 *** warning *** pulse rise time is  < or = zero, reset to tstep


 *** warning *** pulse fall time is  < or = zero, reset to tstep

1 ******  HSPICE W-2005.03        (20050128) 12:35:41  11/23/2008  pcnt         
 ******  
 wire delay model                                                              
  ******  circuit element summary          tnom=  25.000 temp=  25.000         
 ******  


 **** resistors

  
 element name       0:r        
 node1              0:2        
 node2              0:12       
 model                         
 res eff          700.0000     
 tc1                0.         
 tc2                0.         
 scale              1.0000     
 m                  1.0000     
 ac               700.0000     
 temp              25.0000     
 l                  0.         
 w                  0.         
 cap                0.         
 noise              1.0000     


 **** capacitors
  
 element name       0:c1           0:c2       
 node1              0:3            0:12       
 node2              0:0            0:0        
 model                                        
 cap eff          155.0000f      155.0000f    
 tc1                0.             0.         
 tc2                0.             0.         
 scale              1.0000         1.0000     
 ic                 0.             0.         
 m                  1.0000         1.0000     
 w                  0.             0.         
 l                  0.             0.         
 temp              25.0000        25.0000     


 **** independent sources

     name         node1        node2      dc volt    ac mag    ac phase    type
        0:vdd            0:vd             0:0           5.0000     0.         0.      dc   
        0:vx             0:1              0:0           0.         0.         0.      pulse
             initial value     0.     
             pulsed value.     5.0000 
             delay time...     0.     
             risetime.....    10.0000p
             falltime.....    10.0000p
             width........    10.0000n
             period.......    20.0000n



 **** mosfets
  
 element name       2:mp           2:mn           3:mp           3:mn       
 drain              1:1            1:1            0:2            0:2        
 gate               0:1            0:1            1:1            1:1        
 source             0:vd           0:0            0:vd           0:0        
 bulk               0:vd           0:0            0:vd           0:0        
 model              0:mod2         0:mod1         0:mod2         0:mod1     
 w eff             96.0000u       32.0000u       96.0000u       32.0000u    
 l eff            680.0000n      680.0000n      680.0000n      680.0000n    
 rd eff             0.             0.             0.             0.         
 rs eff             0.             0.             0.             0.         
 cdsat             10.0000f       10.0000f       10.0000f       10.0000f    
 cssat             10.0000f       10.0000f       10.0000f       10.0000f    
 capbd              0.             0.             0.             0.         
 capbs              0.             0.             0.             0.         
 temp              25.0000        25.0000        25.0000        25.0000     
 aic                                                                        
  


 **** subcircuit calls
    name        subcircuit         external nodes


         0:xbuffer1 buffer          0:1           0:2       
         1:xint1    inverter        0:1           1:1       
         1:xint2    inverter        1:1           0:2       


 **warning**  only 1 connection at node        0:3                defined in subckt 0               


        : called in element     0:c1 defined in subckt 0                at line    55
           within the hspice source, library or include file 
  Opening plot unit= 79
 file=f:\vlsi\wire\wiredelay.pa0                                               

1 ******  HSPICE W-2005.03        (20050128) 12:35:41  11/23/2008  pcnt         
 ******  
 wire delay model                                                              
  ******  operating point information      tnom=  25.000 temp=  25.000         
 ******  
 ***** operating point status is voltage   simulation time is     0.     
    node    =voltage      node    =voltage      node    =voltage

 +0:1       =   0.      0:2       =   1.1865n 0:3       =   0.     
 +0:12      =   1.1865n 0:vd      =   5.0000  1:1       =   5.0000 

  Opening plot unit= 79
 file=f:\vlsi\wire\wiredelay.tr0                                               

 ******  
 wire delay model                                                              
  ******  transient analysis               tnom=  25.000 temp=  25.000         
 ******  
   delay1=  1.1553E-10  targ=  1.2053E-10   trig=  5.0000E-12
   delay2=  1.1367E-10  targ=  2.0119E-08   trig=  2.0005E-08

          ***** job concluded
1 ******  HSPICE W-2005.03        (20050128) 12:35:41  11/23/2008  pcnt         
 ******  
 wire delay model                                                              
  ******  job statistics summary           tnom=  25.000 temp=  25.000         
 ******  

           total memory used        154 kbytes

  # nodes =     7 # elements=    10
  # diodes=     0 # bjts    =     0 # jfets   =     0 # mosfets =     4

     analysis      time      # points  tot. iter  conv.iter

     op point          0.01         1         7
     transient         0.17     10001      5045      2302 rev=    69
     readin            0.01
     errchk            0.02
     setup             0.00
     output            0.00
           total cpu time          0.21 seconds
               job started at  12:35:41  11/23/2008
               job ended   at  12:35:41  11/23/2008


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