wire.sp

分析集成电路中线间电容的一个小例子

wire model
.opt list acct limpts=1000

.global vd
Vdd vd 0 5


.subckt inverter1 in out
Mp out in vd vd MOD2 W=96u L=0.8u
Mn out in 0   0   MOD1 W=32u L=0.8u
.ends inverter1

.subckt inverter2 in out
Mp out in vd vd MOD2 W=192u L=0.8u
Mn out in 0   0   MOD1 W=64u L=0.8u
.ends inverter2

.subckt buffer in out
Xint1 in 1 inverter1
Xint2 1 out inverter2
.ends buffer

.MODEL  MOD1  NMOS  VTO=1.0  KP=4.5E-5  LAMBDA=0  GAMMA=0.4
+TOX=1.0E-7  NSUB=4.0E+15  LD=0.06U  CJ=2.0E-4  MJ=0.5  
+CJSW=2.0E-10  MJSW=0.4	CGSO=1E-10	CGDO=1E-10	  CGBO=2E-9
.MODEL  MOD2  PMOS  VTO=-1.2  KP=2.5E-5  LAMBDA=0  GAMMA=0.4
+TOX=1.0E-7  NSUB=4.0E+15  LD=0.06U  CJ=2.0E-4  MJ=0.5  
+CJSW=2.0E-10  MJSW=0.4	CGSO=1E-10	CGDO=1E-10	  CGBO=2E-9

Xbuffer1 1  2  buffer
Xbuffer2 13 14 buffer
R1 2 3 70
R2 3 4 70
R3 4 5 70
R4 5 6 70
R5 6 7 70
R6 7 8 70
R7 8 9 70
R8 9 10 70
R9 10 11 70
R10 11 12 70
R11 14 15 70
R12 15 16 70
R13 16 17 70
R14 17 18 70
R15 18 19 70
R16 19 20 70
R17 20 21 70
R18 21 22 70
R19 22 23 70
R20 23 24 70
C1 3 0 31f
C2 4 0 31f
C3 5 0 31f
C4 6 0 31f
C5 7 0 31f
C6 8 0 31f
C7 9 0 31f
C8 10 0 31f
C9 11 0 31f
C10 12 0 31f
C11 15 0 31f
C12 16 0 31f
C13 17 0 31f
C14 18 0 31f
C15 19 0 31f
C16 20 0 31f
C17 21 0 31f
C18 22 0 31f
C19 23 0 31f
C20 24 0 31f
C21 3 15 53f
C22 4 16 53f
C23 5 17 53f
C24 6 18 53f
C25 7 19 53f
C26 8 20 53f
C27 9 21 53f
C28 10 22 53f
C29 11 23 53f
C30 12 24 53f
Vx 1 0 pulse( 0 5 0 0 0 10NS 20NS )
Vxx 13 0 PWL(0NS 0 20NS 0 21NS 5 80NS 5 81NS 0 )
.TRAN 0.01NS 100NS
.print tran v(1)
.plot tran v(1)
.PROBE
.END