5416.h

TMS320VC5416开发板上

//-----------CPU-------------//
#define		IMR	0x0000
#define		IFR	0x0001
#define		ST0	0x0006
#define		ST1	0x0007
#define		AL	0x0008
#define		AH	0x0009
#define		AG	0x000A
#define		BL	0x000B
#define		BH	0x000C
#define		BG	0x000D
#define		TREG	0x000E
#define		TRN	0x000F
#define		AR0	0x0010
#define		AR1	0x0011
#define		AR2	0x0012
#define		AR3	0x0013
#define		AR4	0x0014
#define		AR5	0x0015
#define		AR6	0x0016
#define		AR7	0x0017
#define		SP	0x0018
#define		BK	0x0019
#define		BRC	0x001A
#define		RSA	0x001B
#define		REA	0x001C
#define		PMST	0x001D
#define		XPC	0x001E
#define		TIM	0x0024
#define		PRD	0x0025
#define		TCR	0x0026
#define		SWWSR	0x0028
#define		BSCR	0x0029
#define		SWCR	0x002B
#define		HIPC	0x002C

//-----------CPU-------------//

//-----------MMR-------------//
/*-----------MCBSP-----------*/	
#define		SPSA_ADDR2	0x34
#define		SPSD_ADDR2  0x35
#define		DDR2_ADDR2	0x30
#define		DDR1_ADDR2	0x31
#define		DXR2_ADDR2	0x32
#define		DXR1_ADDR2	0x33

#define		SPSA_ADDR1	0x48
#define		SPSD_ADDR1  0x49
#define		DDR2_ADDR1  0x40
#define		DDR1_ADDR1	0x41
#define		DXR2_ADDR1	0x42
#define		DXR1_ADDR1	0x43

#define		SPSA_ADDR0	0x38
#define		SPSD_ADDR0  0x39
#define		DDR2_ADDR0	0x20
#define		DDR1_ADDR0	0x21
#define		DXR2_ADDR0	0x22
#define		DXR1_ADDR0	0x23

/*-----------MCBSP-----------*/


/*-----------MCBSP_Subaddresses-----------*/
#define		SPCR1_SUBADDR	0x00
#define		SPCR2_SUBADDR	0x01
#define		RCR1_SUBADDR	0x02
#define		RCR2_SUBADDR	0x03
#define		XCR1_SUBADDR	0x04
#define		XCR2_SUBADDR	0x05
#define		SRGR1_SUBADDR	0x06
#define		SRGR2_SUBADDR	0x07
#define		MCR1_SUBADDR	0x08
#define		MCR2_SUBADDR	0x09
#define		RCERA_SUBADDR	0x0A
#define		RCERB_SUBADDR	0x0B
#define		XCERA_SUBADDR	0x0C
#define		XCERB_SUBADDR	0x0D
#define		PCR_SUBADDR	    0x0E
#define		RCERC_SUBADDR	0x0010
#define		RCERD_SUBADDR	0x0011
#define		XCERC_SUBADDR	0x0012
#define		XCERD_SUBADDR	0x0013
#define		RCERE_SUBADDR	0x0014
#define		RCERF_SUBADDR	0x0015
#define		XCERE_SUBADDR	0x0016
#define		XCERF_SUBADDR	0x0017
#define		RCERG_SUBADDR	0x0018
#define		RCERH_SUBADDR	0x0019
#define		XCERG_SUBADDR	0x001A
#define		XCERH_SUBADDR	0x001B
/*-----------MCBSP_Subaddresses-----------*/

#define		CLKMD		0x0058

/*-----------DMA-----------*/
#define		DMPREC		0x0054
#define		DMSA		0x0055
#define		DMSDI		0x0056
#define		DMSDN		0x0057

#define		DMSRC0		0x00
#define		DMDST0		0x01
#define		DMCTR0		0x02
#define		DMSFC0		0x03
#define		DMMCR0		0x04
#define		DMSRC1		0x05
#define		DMDST1		0x06
#define		DMCTR1		0x07
#define		DMSFC1		0x08
#define		DMMCR1		0x09
#define		DMSRC2		0x0A
#define		DMDST2		0x0B
#define		DMCTR2		0x0C
#define		DMSFC2		0x0D
#define		DMMCR2		0x0E
#define		DMSRC3		0x0F
#define		DMDST3		0x10
#define		DMCTR3		0x11
#define		DMSFC3		0x12
#define		DMMCR3		0x13
#define		DMSRC3		0x0F
#define		DMDST3		0x10
#define		DMCTR3		0x11
#define		DMSFC3		0x12
#define		DMMCR3		0x13
#define		DMSRC4		0x14
#define		DMDST4		0x15
#define		DMCTR4		0x16
#define		DMSFC4		0x17
#define		DMMCR4		0x18
#define		DMSRC5		0x19
#define		DMDST5		0x1A
#define		DMCTR5		0x1B
#define		DMSFC5		0x1C
#define		DMMCR5		0x1D
#define		DMSRCP		0x1E
#define		DMSTP		0x1F
#define		DMIDX0		0x20
#define		DMIDX1		0x21
#define		DMFRI0		0x22
#define		DMFRI1		0x23
#define		DMGSA		0x24
#define		DMGDA		0x25
#define		DMGCR		0x26
#define		DMGFR		0x27



/*-----------DMA-----------*/