gspx-pxa.c

Wince BSP 下的Wifi 驱动 基于PXA270 CPU

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  

pxa-gspi.c

Abstract:  

Holds implementation of pcmcia serial driver interface.  This serial PDD
makes use of the ser16550 library to do most of the work.

Functions:


Notes: 


--*/

#ifdef PXA270_SPI
#include <windows.h>
#include <nkintr.h>
#include <ndis.h>

#include <types.h>
#include <memory.h>
#include <tchar.h>

#include <ceddk.h>
#include <bulverde.h>

#include <xllp_dmac.h>
#include <Devload.h>

#include <giisr.h>
#include "dbg.h"
#include "myintr.h"
#include "pxa-gpio.h"
#include "pxa-ssp.h"
#include "pxa-dma.h"
#include "JaguarGSPX.h"
#include "gspx-pxa.h"
#include "sspioctl.h"

//copied from Sandgateii\Src\Kernel\Oal\intr.c
#define IRQ_GPIO17_EXPBD              (IRQ_BULVERDE_MAX + 8)   // 39

#ifdef DEBUG
	#define		GSPIMSG		DEBUGMSG
#else
	#define		GSPIMSG		RETAILMSG
#endif ///DEBUG

///int		g_fmDnRdy = FALSE;
//###xlin
#ifndef __FUNCTION__
#define __FUNCTION__ " "
#endif
//JKU: extern int		g_spi_dummy_clk_reg;
int             g_spi_dummy_clk_reg = 0x05;   //JKU
//JKU: extern int		g_spi_dummy_clk_data;
int     		g_spi_dummy_clk_data = 0x0e;

static LPCTSTR pg_szActiveKey = _T("GSPI8385");

///============================================================================
/// Flags to control the displayed message
#define		ERRMSG		0			///Error Message. Displayed only error occurred
#define		FUNCTAG		0			///Display the message to show the function enter/exit
#define		TICKCNTMSG	0			///Tick count message
#define		PROGFLOW	0			///Display the message to show the program's running flow
#define		TX_FRAG	0			///Display the message whenever the fragmentation is needed in TX
#define		RX_FRAG	0			///Display the message whenever the fragmentation is needed in RX
#define		DMA_MSG		0			///Display the message for debuggin the DMA module
///============================================================================
#define ENTERFUNC()		GSPIMSG(FUNCTAG,(L"Enter %s\n", TEXT(__FUNCTION__)))
#define EXITFUNC(x)		GSPIMSG(FUNCTAG, (L"Exit %s (%d)\n", TEXT(__FUNCTION__), x))



#define	GSPI_MAX_REG_RETRY		3

static GSPI_STATUS setup_write_dma(PSSP_HARDWARE_CONTEXT pHC, int n);
static GSPI_STATUS setup_read_dma(PSSP_HARDWARE_CONTEXT pHC, int n);
///////////////////////////////////////////////////////////////////////////////
//###xlin 
//SSP1 for Cherubim
#define SSPCTRLER 1
//to use DEVIRQ 
#define USE_DEVIRQ 1
//for 8686 chip
#define GSPI8686 1
#if (SSPCTRLER == 1)
#define		SSPREG_PHY_BASE		BULVERDE_BASE_REG_PA_SSP1
#define		DMA_CHMAP_SSP_RX	DMA_CHMAP_SSP1_RX
#define		DMA_CHMAP_SSP_TX	DMA_CHMAP_SSP1_TX

#define		XLLP_DMAC_SSP_RX	XLLP_DMAC_SSP_1_RX
#define		XLLP_DMAC_SSP_TX	XLLP_DMAC_SSP_1_TX
#elif (SSPCTRLER == 2)
#define		SSPREG_PHY_BASE		BULVERDE_BASE_REG_PA_SSP2
#define		DMA_CHMAP_SSP_RX	DMA_CHMAP_SSP2_RX
#define		DMA_CHMAP_SSP_TX	DMA_CHMAP_SSP2_TX

#define		XLLP_DMAC_SSP_RX	XLLP_DMAC_SSP_2_RX
#define		XLLP_DMAC_SSP_TX	XLLP_DMAC_SSP_2_TX
#elif (SSPCTRLER == 3)
#define		SSPREG_PHY_BASE		BULVERDE_BASE_REG_PA_SSP3
#define		DMA_CHMAP_SSP_RX	DMA_CHMAP_SSP3_RX
#define		DMA_CHMAP_SSP_TX	DMA_CHMAP_SSP3_TX

#define		XLLP_DMAC_SSP_RX	XLLP_DMAC_SSP_3_RX
#define		XLLP_DMAC_SSP_TX	XLLP_DMAC_SSP_3_TX
#endif ///SSPCTRLER



///---------------------------------------------------------
///Signal Definition
///
#define		SSP_SCLK			23
#define		SSP_SFRM			24
#define		SSP_TX				25
#define		SSP_RX				26
#define		SSP_INTR			17
#define		SSP_RST				11
#ifdef USE_TEST_PIN
#define		SSP_TST1			14
#define		SSP_TST2			19
#define		SSPTST1_ATTR		GPIO_OUT		
#define		SSPTST2_ATTR		GPIO_OUT		
#endif
#define		SSPSCLK_ATTR		GPIO_ALT_FN_2_OUT
#define		SSPSFRM_ATTR		GPIO_OUT
#define		SSPTX_ATTR			GPIO_ALT_FN_2_OUT
#define		SSPRX_ATTR			GPIO_ALT_FN_1_IN
#define		SSPIRQ_ATTR			GPIO_IN

#define		SSPRESET_ATTR			GPIO_OUT


///Define DMA channel
#define		DMA_CH_READ			8
#define		DMA_CH_RW			24

///#define		SSP_IRQNUM			22			///Trial value from sdhc_mainstoneii.reg

#define		MVL_DEF_DRR			0x05
#define		MVL_DEF_DRP			0x0e
///CLK dividend
static int clkdiv = 0;

///---------------------------------------------------------
///Buffer defintion
///
#define PXA_SSP_BLKSZ_MAX				(1<<9)
#define PXA_SSP_BLOCKS_PER_BUFFER		(3)
#define PXA_SSP_IODATA_SIZE				(PXA_SSP_BLOCKS_PER_BUFFER * \
											PXA_SSP_BLKSZ_MAX)

///---------------------------------------------------------
///DMA ISR functions
///
/// Maximum waiting period (us)
#define		MAX_WAITus		100000   //dralee 100ms
///#define		MAX_WAITus		10000000   //dralee 100ms

// the dmcd struct is for documentation
struct dcmdRegBits 
{
    unsigned len         :13;
    unsigned rsv0        :1;   
    unsigned width       :2; 
    unsigned size        :2;
    unsigned endian      :1;
    unsigned flybyt      :1;
    unsigned flybys      :1;
    unsigned endirqen    :1;
    unsigned startirqen  :1;
    unsigned rsv1        :5;
    unsigned flowtrg     :1;
    unsigned flowsrc     :1;
    unsigned inctrgadd   :1;
    unsigned incsrcadd   :1;
};

union DMACmdReg// allow bitfields or masks
{
    volatile struct dcmdRegBits DcmdReg ;
    volatile DWORD DcmdDword;
} ;

//#define DEFAULT_IST_PRIORITY 101
///#define DEFAULT_IST_PRIORITY 249
///#define SSP_DMA_INTR					(SYSINTR_FIRMWARE+1)
///#define SSP_DMA_INTR					(SYSINTR_FIRMWARE+1)


///static ULONG dma_irqr(PSSP_HARDWARE_CONTEXT	pHC);
///static ULONG dma_irqw(VOID* devid);
static BOOLEAN dma_ist(LPVOID param);
static BOOLEAN dev_ist(PSSP_HARDWARE_CONTEXT	pHC);

static GSPI_STATUS ssp_write_data_direct(PVOID hDC, PWORD data, WORD reg, WORD nword);
static GSPI_STATUS ssp_read_data_direct(PVOID hDC, WORD* data, WORD reg, WORD nword, WORD dummy_clk);
//JKU: int gspx_set_callback(PVOID pHC, PVOID cb, void *data);

///---------------------------------------------------------
//The function was modified from XllpOstDelayMicroSeconds() in XLLP\xllp_ost.c
//
// OST Tick constants
//
#define XLLP_OST_TICKS_MS    3250          // 1ms in ticks (3.25x10^6tick/sec * 1/1000sec/msec)
#define XLLP_OST_TICKS_US    3             // 1usec in ticks (3.25x10^6tick/sec * 1/1000000sec/usec)
#ifdef USE_TEST_PIN
PSSP_HARDWARE_CONTEXT pLocalHC;
void GspiHostSetTst1High()
{
	PSSP_HARDWARE_CONTEXT pContext = (PSSP_HARDWARE_CONTEXT) pLocalHC;
	set_GPIO_signal(pContext->pGPIORegs, SSP_TST1, SIG_UP);
}

void GspiHostSetTst1Low()
{
	PSSP_HARDWARE_CONTEXT pContext = (PSSP_HARDWARE_CONTEXT) pLocalHC;
	set_GPIO_signal(pContext->pGPIORegs, SSP_TST1, SIG_DOWN);	
}

void GspiHostSetTst2Low()
{

	PSSP_HARDWARE_CONTEXT pContext = (PSSP_HARDWARE_CONTEXT) pLocalHC;
	set_GPIO_signal(pContext->pGPIORegs, SSP_TST2, SIG_DOWN);	
}
void GspiHostSetTst2High()
{
	PSSP_HARDWARE_CONTEXT pContext = (PSSP_HARDWARE_CONTEXT) pLocalHC;
	set_GPIO_signal(pContext->pGPIORegs, SSP_TST2, SIG_UP);	
}
#endif

static void XllpOstDelayTicks 
     (volatile BULVERDE_OST_REG * pOstRegs, DWORD ticks)
{   
 
	volatile DWORD    expireTime;
	volatile DWORD    time=0;
	time = pOstRegs->oscr0;
	expireTime = time + ticks;

	//
	// Check if we wrapped on the expireTime
	// and delay first part until wrap
	//   
	if (expireTime < time) 
	{
		while (time <= pOstRegs->oscr0);
        }
	while (pOstRegs->oscr0 <= expireTime);   


    return;
}

void udelay(volatile BULVERDE_OST_REG *pOstRegs, DWORD ms)
{
	DWORD		ticks;

	ticks = ms * XLLP_OST_TICKS_US * 3;  // approx. 3 ticks per microsecond. 
	XllpOstDelayTicks (pOstRegs, ticks);
	return;
}



///////////////////////////////////////////////////////////////////////////////
/// Core functions of the SSP interface accessing
/// 
static GSPI_STATUS setup_write_dma(PSSP_HARDWARE_CONTEXT pHC, int n)
{
	GSPI_STATUS		result = GSPI_SUCCESS;
	volatile DMADescriptorChannelType *desc = pHC->write_desc;
	MYDMAPARAM		*pDmaParam = &pHC->DMAParam[WTDMA_PARAM];
	#if (USE_DMAIRQ == 1)
	DWORD			dmaresult;
	#endif ///USE_DMAIRQ

	desc->ddadr |= DDADR_STOP;
	desc->dcmd &= ~(DCMD_LENGTH);

	#if (USE_DMAIRQ == 1)
	desc->dcmd |= DCMD_ENDIRQEN | n;
	ResetEvent(pDmaParam->dmaWaitObj);
	#else ///USE_DMAIRQ
	desc->dcmd |= n;
	#endif ///USE_DMAIRQ
	if (n > PXA_SSP_IODATA_SIZE) {
		GSPIMSG(ERRMSG, (TEXT("Requested length is too large (limit, req) = (%d, %xh)\n"), ERRMSG, n));
	}

	///Start DMA channel
	pHC->pDMARegs->ddg[pDmaParam->channel].ddadr = (UINT32) pHC->write_desc_phys_addr;
	pHC->pDMARegs->dcsr[pDmaParam->channel] |=  DCSR_RUN;		/// set the RUN bit

	///Wait here until it's done
	#if (USE_DMAIRQ == 1)
	dmaresult = WaitForSingleObject(pDmaParam->dmaWaitObj, (MAX_WAITus/1000));
	if (dmaresult == WAIT_TIMEOUT) {
		GSPIMSG(ERRMSG, (TEXT("Wt-DMA timeout (%d)\n"), n));
		result = GSPI_TIMEOUT;
		///goto funcFinal;
	}
	#else	///USE_DMAIRQ
	///Wait here until it's done
	{
		int		lp;
		volatile DWORD	dcsr;
		for (lp=0 ; lp<MAX_WAITus ; lp++) {			///Trial period (1s)
			dcsr = pHC->pDMARegs->dcsr[pDmaParam->channel];
			if (dcsr & (DCSR_STOPSTATE)) {
				///GSPIMSG(1, (TEXT("wt(%d) (lp,dcsr) = (%d, %xh)\n"), n, lp, dcsr));
				break;
			}
			udelay(pHC->pOSTRegs, 1);
			///NdisMSleep(1);
			///for (a=0 ; a<10 ; a++) ;
		}
		if (lp == MAX_WAITus) {
			GSPIMSG(ERRMSG, (TEXT("Wt-DMA(%d) (lp, dcsr) = (%d, %xh)\n"), n, lp, dcsr));
			result = GSPI_TIMEOUT;
		///} else {
			///GSPIMSG(1, (TEXT("Wt-DMA ok, dcsr= %xh\n"), dcsr));
		}
		///Add one more delay at the end. Otherwise, the firmware download will failed. 
		/// (Don't know why)
		udelay(pHC->pOSTRegs, 50);			///Trial value
		///NdisMSleep(1);
	}
	#endif ///USE_DMAIRQ
///funcFinal:
	return result;
}

static GSPI_STATUS ssp_write_data_direct(PVOID hDC, PWORD data, WORD reg, WORD nword)
{
	int		result = GSPI_SUCCESS;
	PSSP_HARDWARE_CONTEXT	pHC;
#if (USE_DMA == 1)
 	int		nbyte;
	///crlo:length-fix ++
	int		fragnbyte, accnbyte;  //JKU: uncomment if use Marvell's code
#endif
	BOOLEAN	 needToWriteReg = TRUE;
	BOOLEAN		isFrag = FALSE;
	///crlo:length-fix --

#if (USE_DMA != 1)
	int		i;
#endif ///(USE_DMA == 1)
	ENTERFUNC();
	if (hDC == 0) {
		result = GSPI_INVALIDARGS;
		goto funcLeave;
	}
	pHC = (PSSP_HARDWARE_CONTEXT)hDC;

	EnterCriticalSection(&pHC->SSPCrit);


    //DEBUGMSG(ZONE_INIT, (TEXT("[w+][%x]<=%d,%x\n"),reg,nword,*data));

	///n is a unit of WORD. Convert it to unit of BYTE
	reg |= 0x8000;

#if !(USE_DMA == 1)
	while ((pHC->pSSPRegs->base.ssr & 4) == 0);	//check TNF
	while (pHC->pSSPRegs->base.ssr & 0xF00);	//check TFL
#endif
	set_GPIO_signal(pHC->pGPIORegs, SSP_SFRM,SIG_UP);
	set_GPIO_signal(pHC->pGPIORegs, SSP_SFRM,SIG_DOWN);	

#if (USE_DMA == 1)
       nbyte = nword*2;
       memcpy(pHC->iodata, (PBYTE) &reg, sizeof(WORD));
       memcpy(pHC->iodata + sizeof(WORD), (PBYTE) data, nbyte);
		//memcpy(pHC->iodata, data, nword*2);
		result = setup_write_dma(pHC, nbyte+2);
		if (result != GSPI_SUCCESS) 
       {
			GSPIMSG(ERRMSG, (TEXT("Not successful after sending %d bytes.\n"), accnbyte));
		}
#else
	pHC->pSSPRegs->base.ssdr = reg;

	for (i=0; i<nword; i++)
	{
		while ((pHC->pSSPRegs->base.ssr & 4) == 0);	//check TNF
		pHC->pSSPRegs->base.ssdr = *data++;
	}