exp_cpu_pt_vhd.tcl

计算机体系结构试验

## Copyright (C) 1991-2006 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.

## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

## DATE "03/22/2007 10:50:05"

## 
## Device: Altera EP1C6Q240C8 Package PQFP240
## 

## 
## This Tcl script should be used for PrimeTime (VHDL) only
## 

## This file can be sourced in primetime

set report_default_significant_digits 3
set hierarchy_separator .

set quartus_root "c:/altera/quartus60/"
set search_path [list . [format "%s%s" $quartus_root "eda/synopsys/primetime/lib"]  ]

set link_path [list *  cyclone_asynch_io_lib.db cyclone_asynch_lcell_lib.db  cyclone_core_mem_lib.db cyclone_lcell_register_lib.db  cyclone_memory_register_lib.db  cyclone_pll_lib.db  alt_vtl.db]

read_vhdl  -vhdl_compiler  cyclone_all_pt.vhd 

##########################
## DESIGN ENTRY SECTION ##
##########################

read_vhdl  -vhdl_compiler exp_cpu.vho
current_design exp_cpu
link
## Set variable timing_propagate_single_condition_min_slew to false only for versions 2004.06 and earlier
regexp {([1-9][0-9][0-9][0-9]\.[0-9][0-9])} $sh_product_version dummy version
if { [string compare "2004.06" $version ] != -1 } {
   set timing_propagate_single_condition_min_slew false
}
set_operating_conditions -analysis_type single
read_sdf exp_cpu_vhd.sdo

################################
## TIMING CONSTRAINTS SECTION ##
################################


## Start clock definition ##
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { clk } ] -name clk  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { reset } ] -name reset  

set_propagated_clock [all_clocks]
set_clock_groups -asynchronous \
-group {clk} \
-group {reset}
## End clock definition ##

## Start create collections ##
## End create collections ##

## Start global settings ##
## End global settings ##

## Start collection commands definition ##

## End collection commands definition ##

## Start individual pin commands definition ##
## End individual pin commands definition ##

## Start Output pin capacitance definition ##
# Warning:  Using default load capacitance for LVTTL output port.
set_load -pin_load 10 [get_ports { reg_content[0] reg_content[1] reg_content[2] reg_content[3] reg_content[4] reg_content[5] reg_content[6] reg_content[7] reg_content[8] \
    reg_content[9] reg_content[10] reg_content[11] reg_content[12] reg_content[13] reg_content[14] reg_content[15] c_flag z_flag WE AR[0] AR[1] AR[2] AR[3] AR[4] AR[5] AR[6] AR[7] \
    AR[8] AR[9] AR[10] AR[11] AR[12] AR[13] AR[14] AR[15] OB[1] OB[10] OB[11] OB[12] OB[13] OB[14] OB[15] OB[2] OB[0] OB[9] OB[8] OB[3] OB[4] OB[5] OB[6] OB[7] } ]
## End Output pin capacitance definition ##

## Start clock uncertainty definition ##
## End clock uncertainty definition ##

## Start Multicycle and Cut Path definition ##
## End Multicycle and Cut Path definition ##

## Destroy Collections ##

update_timing