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📄 exp_cpu.vho

📁 计算机体系结构试验
💻 VHO
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SIGNAL \G_REGFILE|Areg01|q_output[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~540_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~540_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~280_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~280_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~302_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~302_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux9~32_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux9~32_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux9~33_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux9~33_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux9~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux9~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux9~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux9~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux8~14_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux8~14_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~567_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~567_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux6~14_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux6~14_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~569_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~569_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux7~28_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux7~28_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux8~36_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux8~36_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~568_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~568_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~542_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~542_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~282_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~282_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~304_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~304_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux8~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux8~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux8~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux8~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux8~37_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux8~37_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~544_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~544_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~284_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~284_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~306_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~306_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux7~32_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux7~32_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux7~33_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux7~33_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux7~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux7~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux7~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux7~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~546_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~546_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~286_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~286_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~308_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~308_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux6~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux6~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux6~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux6~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux6~37_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux6~37_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux2~14_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux2~14_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~572_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~572_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux4~14_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux4~14_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~571_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~571_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~548_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~548_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~288_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~288_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~310_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~310_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux5~32_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux5~32_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux5~33_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux5~33_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux5~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux5~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux5~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux5~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~550_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~550_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux4~36_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux4~36_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~290_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~290_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~312_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~312_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux4~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux4~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux4~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux4~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux4~37_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux4~37_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux3~21_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux3~21_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~292_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~292_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~314_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~314_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux3~32_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux3~32_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux3~33_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux3~33_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~573_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~573_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~552_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~552_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux3~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux3~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux3~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux3~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|z_out~191_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|z_out~191_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux0~14_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux0~14_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~575_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~575_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux1~21_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux1~21_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux2~36_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux2~36_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~574_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~574_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
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