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📄 exp_cpu.vho

📁 计算机体系结构试验
💻 VHO
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SIGNAL \G_REGFILE|Areg01|q_output[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux16~75_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux16~75_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux16~73_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux16~73_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux16~74_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux16~74_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux16~76_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux16~76_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux15~323_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux15~323_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux15~321_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux15~321_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux15~324_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux15~324_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux15~317_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux15~317_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux15~320_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux15~320_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|pc_inc[0]~32_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|pc_inc[0]~32_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|sjmp_addr[0]~32_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|sjmp_addr[0]~32_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_DECODER|Mux1~19_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_DECODER|Mux1~19_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux13~20_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux13~20_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux14~36_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux14~36_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~562_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~562_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~530_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~530_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~292_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~292_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~270_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~270_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux14~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux14~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux14~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux14~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux14~37_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux14~37_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux10~14_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux10~14_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux11~20_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux11~20_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~564_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~564_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux12~14_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux12~14_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~563_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~563_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~532_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~532_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~294_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~294_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~272_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~272_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux13~89_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux13~89_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux13~90_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux13~90_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux13~91_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux13~91_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux13~92_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux13~92_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~534_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~534_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux12~36_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux12~36_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~296_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~296_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~274_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~274_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux12~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux12~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux12~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux12~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux12~37_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux12~37_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~276_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~276_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~298_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~298_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux11~32_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux11~32_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux11~33_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux11~33_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~565_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~565_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~536_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~536_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux11~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux11~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux11~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux11~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|z_out~189_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|z_out~189_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux5~20_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux5~20_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux6~36_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux6~36_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~570_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~570_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux9~20_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux9~20_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~566_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~566_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~538_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~538_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux10~36_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux10~36_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~300_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~300_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~278_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~278_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux10~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux10~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux10~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux10~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux10~37_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux10~37_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
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