exp_cpu.vho

计算机体系结构试验

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

-- DATE "03/22/2007 10:50:04"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	exp_cpu IS
    PORT (
	clk : IN std_logic;
	reset : IN std_logic;
	reg_sel : IN std_logic_vector(5 DOWNTO 0);
	reg_content : OUT std_logic_vector(15 DOWNTO 0);
	c_flag : OUT std_logic;
	z_flag : OUT std_logic;
	WE : OUT std_logic;
	AR : OUT std_logic_vector(15 DOWNTO 0);
	OB : INOUT std_logic_vector(15 DOWNTO 0)
	);
END exp_cpu;

ARCHITECTURE structure OF exp_cpu IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_reg_sel : std_logic_vector(5 DOWNTO 0);
SIGNAL ww_reg_content : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_c_flag : std_logic;
SIGNAL ww_z_flag : std_logic;
SIGNAL ww_WE : std_logic;
SIGNAL ww_AR : std_logic_vector(15 DOWNTO 0);
SIGNAL \OB[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[1]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[2]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[3]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[4]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[5]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[6]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[7]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[8]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[9]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[10]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[11]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[12]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[13]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[14]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \OB[15]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \reg_sel[3]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \reg_sel[4]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \reg_sel[5]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \reg_sel[2]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \reg_sel[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \Mux15~319_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux15~319_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \reset~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|R_W_Memory_proc~21_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|R_W_Memory_proc~21_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \reg_sel[1]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|start~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|start~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|t1~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|t1~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|t2~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|t2~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|t3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|t3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|comb~0_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|comb~0_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_DECODER|sel_memdata~10_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_DECODER|sel_memdata~10_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_DECODER|DRWr~11_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_DECODER|DRWr~11_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|des_decoder|sel02~86_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|des_decoder|sel02~86_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|des_decoder|sel02~87_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|des_decoder|sel02~87_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg01|q_output[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|des_decoder|sel02~88_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|des_decoder|sel02~88_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux14~14_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|muxA|Mux14~14_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux13~88_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux13~88_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux13~87_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux13~87_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~561_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~561_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg02|q_output[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|process0~0_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|process0~0_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg03|q_output[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~560_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~560_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~526_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~526_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add1~528_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add1~528_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~266_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~266_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add3~268_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add3~268_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_DECODER|op_code[0]~50_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_DECODER|op_code[0]~50_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~288_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~288_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Add4~290_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Add4~290_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux15~32_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux15~32_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux15~33_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux15~33_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux15~34_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux15~34_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_EXE|Mux15~35_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_EXE|Mux15~35_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_REGFILE|Areg00|q_output[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_MEMORY|data_read[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \G_INSTRU_FETCH|IR[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);