exp_cpu.vo

计算机体系结构试验

	.devoe(devoe),
	.combout(\reg_sel~combout [0]),
	.regout(),
	.padio(reg_sel[0]));
// synopsys translate_off
defparam \reg_sel[0]~I .input_async_reset = "none";
defparam \reg_sel[0]~I .input_power_up = "low";
defparam \reg_sel[0]~I .input_register_mode = "none";
defparam \reg_sel[0]~I .input_sync_reset = "none";
defparam \reg_sel[0]~I .oe_async_reset = "none";
defparam \reg_sel[0]~I .oe_power_up = "low";
defparam \reg_sel[0]~I .oe_register_mode = "none";
defparam \reg_sel[0]~I .oe_sync_reset = "none";
defparam \reg_sel[0]~I .operation_mode = "input";
defparam \reg_sel[0]~I .output_async_reset = "none";
defparam \reg_sel[0]~I .output_power_up = "low";
defparam \reg_sel[0]~I .output_register_mode = "none";
defparam \reg_sel[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X12_Y13_N8
cyclone_lcell \Mux15~319_I (
// Equation(s):
// \Mux15~319  = \reg_sel~combout [3] & (\reg_sel~combout [0]) # !\reg_sel~combout [3] & \reg_sel~combout [2]

	.clk(gnd),
	.dataa(\reg_sel~combout [2]),
	.datab(\reg_sel~combout [3]),
	.datac(vcc),
	.datad(\reg_sel~combout [0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux15~319 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux15~319_I .lut_mask = "EE22";
defparam \Mux15~319_I .operation_mode = "normal";
defparam \Mux15~319_I .output_mode = "comb_only";
defparam \Mux15~319_I .register_cascade_mode = "off";
defparam \Mux15~319_I .sum_lutc_input = "datac";
defparam \Mux15~319_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X19_Y11_N5
cyclone_lcell \G_MEMORY|data_read[12]~I (
// Equation(s):
// \G_MEMORY|data_read [12] = GLOBAL(\G_MEMORY|comb~0 ) & \OB[12]~3  # !GLOBAL(\G_MEMORY|comb~0 ) & (\G_MEMORY|data_read [12])

	.clk(gnd),
	.dataa(\OB[12]~3 ),
	.datab(\G_MEMORY|data_read [12]),
	.datac(vcc),
	.datad(\G_MEMORY|comb~0 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\G_MEMORY|data_read [12]),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \G_MEMORY|data_read[12]~I .lut_mask = "AACC";
defparam \G_MEMORY|data_read[12]~I .operation_mode = "normal";
defparam \G_MEMORY|data_read[12]~I .output_mode = "comb_only";
defparam \G_MEMORY|data_read[12]~I .register_cascade_mode = "off";
defparam \G_MEMORY|data_read[12]~I .sum_lutc_input = "datac";
defparam \G_MEMORY|data_read[12]~I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_240
cyclone_io \reset~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\reset~combout ),
	.regout(),
	.padio(reset));
// synopsys translate_off
defparam \reset~I .input_async_reset = "none";
defparam \reset~I .input_power_up = "low";
defparam \reset~I .input_register_mode = "none";
defparam \reset~I .input_sync_reset = "none";
defparam \reset~I .oe_async_reset = "none";
defparam \reset~I .oe_power_up = "low";
defparam \reset~I .oe_register_mode = "none";
defparam \reset~I .oe_sync_reset = "none";
defparam \reset~I .operation_mode = "input";
defparam \reset~I .output_async_reset = "none";
defparam \reset~I .output_power_up = "low";
defparam \reset~I .output_register_mode = "none";
defparam \reset~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X19_Y11_N1
cyclone_lcell \G_INSTRU_FETCH|IR[12]~I (
// Equation(s):
// \G_INSTRU_FETCH|IR [12] = DFFEAS(!\G_MEMORY|data_read [12], GLOBAL(\G_INSTRU_FETCH|t2 ), GLOBAL(\reset~combout ), , , , , , )

	.clk(\G_INSTRU_FETCH|t2 ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\G_MEMORY|data_read [12]),
	.aclr(!\reset~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\G_INSTRU_FETCH|IR [12]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \G_INSTRU_FETCH|IR[12]~I .lut_mask = "00FF";
defparam \G_INSTRU_FETCH|IR[12]~I .operation_mode = "normal";
defparam \G_INSTRU_FETCH|IR[12]~I .output_mode = "reg_only";
defparam \G_INSTRU_FETCH|IR[12]~I .register_cascade_mode = "off";
defparam \G_INSTRU_FETCH|IR[12]~I .sum_lutc_input = "datac";
defparam \G_INSTRU_FETCH|IR[12]~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X19_Y11_N3
cyclone_lcell \G_MEMORY|data_read[15]~I (
// Equation(s):
// \G_MEMORY|data_read [15] = GLOBAL(\G_MEMORY|comb~0 ) & \OB[15]~0  # !GLOBAL(\G_MEMORY|comb~0 ) & (\G_MEMORY|data_read [15])

	.clk(gnd),
	.dataa(vcc),
	.datab(\OB[15]~0 ),
	.datac(\G_MEMORY|data_read [15]),
	.datad(\G_MEMORY|comb~0 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\G_MEMORY|data_read [15]),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \G_MEMORY|data_read[15]~I .lut_mask = "CCF0";
defparam \G_MEMORY|data_read[15]~I .operation_mode = "normal";
defparam \G_MEMORY|data_read[15]~I .output_mode = "comb_only";
defparam \G_MEMORY|data_read[15]~I .register_cascade_mode = "off";
defparam \G_MEMORY|data_read[15]~I .sum_lutc_input = "datac";
defparam \G_MEMORY|data_read[15]~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X19_Y11_N7
cyclone_lcell \G_INSTRU_FETCH|IR[15]~I (
// Equation(s):
// \G_DECODER|op_code[2]~49  = D1_IR[15] # !\G_INSTRU_FETCH|IR [14]
// \G_INSTRU_FETCH|IR [15] = DFFEAS(\G_DECODER|op_code[2]~49 , GLOBAL(\G_INSTRU_FETCH|t2 ), GLOBAL(\reset~combout ), , , \G_MEMORY|data_read [15], , , VCC)

	.clk(\G_INSTRU_FETCH|t2 ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\G_MEMORY|data_read [15]),
	.datad(\G_INSTRU_FETCH|IR [14]),
	.aclr(!\reset~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\G_DECODER|op_code[2]~49 ),
	.regout(\G_INSTRU_FETCH|IR [15]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \G_INSTRU_FETCH|IR[15]~I .lut_mask = "F0FF";
defparam \G_INSTRU_FETCH|IR[15]~I .operation_mode = "normal";
defparam \G_INSTRU_FETCH|IR[15]~I .output_mode = "reg_and_comb";
defparam \G_INSTRU_FETCH|IR[15]~I .register_cascade_mode = "off";
defparam \G_INSTRU_FETCH|IR[15]~I .sum_lutc_input = "qfbk";
defparam \G_INSTRU_FETCH|IR[15]~I .synch_mode = "on";
// synopsys translate_on

// atom is at LC_X23_Y14_N5
cyclone_lcell \G_MEMORY|data_read[13]~I (
// Equation(s):
// \G_MEMORY|data_read [13] = GLOBAL(\G_MEMORY|comb~0 ) & (\OB[13]~2 ) # !GLOBAL(\G_MEMORY|comb~0 ) & \G_MEMORY|data_read [13]

	.clk(gnd),
	.dataa(vcc),
	.datab(\G_MEMORY|data_read [13]),
	.datac(\OB[13]~2 ),
	.datad(\G_MEMORY|comb~0 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\G_MEMORY|data_read [13]),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \G_MEMORY|data_read[13]~I .lut_mask = "F0CC";
defparam \G_MEMORY|data_read[13]~I .operation_mode = "normal";
defparam \G_MEMORY|data_read[13]~I .output_mode = "comb_only";
defparam \G_MEMORY|data_read[13]~I .register_cascade_mode = "off";
defparam \G_MEMORY|data_read[13]~I .sum_lutc_input = "datac";
defparam \G_MEMORY|data_read[13]~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y14_N4
cyclone_lcell \G_INSTRU_FETCH|IR[13]~I (
// Equation(s):
// \G_INSTRU_FETCH|IR [13] = DFFEAS(!\G_MEMORY|data_read [13], GLOBAL(\G_INSTRU_FETCH|t2 ), GLOBAL(\reset~combout ), , , , , , )

	.clk(\G_INSTRU_FETCH|t2 ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\G_MEMORY|data_read [13]),
	.aclr(!\reset~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\G_INSTRU_FETCH|IR [13]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \G_INSTRU_FETCH|IR[13]~I .lut_mask = "00FF";
defparam \G_INSTRU_FETCH|IR[13]~I .operation_mode = "normal";
defparam \G_INSTRU_FETCH|IR[13]~I .output_mode = "reg_only";
defparam \G_INSTRU_FETCH|IR[13]~I .register_cascade_mode = "off";
defparam \G_INSTRU_FETCH|IR[13]~I .sum_lutc_input = "datac";
defparam \G_INSTRU_FETCH|IR[13]~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y13_N9
cyclone_lcell \G_MEMORY|R_W_Memory_proc~21_I (
// Equation(s):
// \G_MEMORY|R_W_Memory_proc~21  = \G_INSTRU_FETCH|IR [12] & \G_INSTRU_FETCH|IR [15] & !\G_INSTRU_FETCH|IR [14] & !\G_INSTRU_FETCH|IR [13]

	.clk(gnd),
	.dataa(\G_INSTRU_FETCH|IR [12]),
	.datab(\G_INSTRU_FETCH|IR [15]),
	.datac(\G_INSTRU_FETCH|IR [14]),
	.datad(\G_INSTRU_FETCH|IR [13]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\G_MEMORY|R_W_Memory_proc~21 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \G_MEMORY|R_W_Memory_proc~21_I .lut_mask = "0008";
defparam \G_MEMORY|R_W_Memory_proc~21_I .operation_mode = "normal";
defparam \G_MEMORY|R_W_Memory_proc~21_I .output_mode = "comb_only";
defparam \G_MEMORY|R_W_Memory_proc~21_I .register_cascade_mode = "off";
defparam \G_MEMORY|R_W_Memory_proc~21_I .sum_lutc_input = "datac";
defparam \G_MEMORY|R_W_Memory_proc~21_I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_13
cyclone_io \reg_sel[1]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\reg_sel~combout [1]),
	.regout(),
	.padio(reg_sel[1]));
// synopsys translate_off
defparam \reg_sel[1]~I .input_async_reset = "none";
defparam \reg_sel[1]~I .input_power_up = "low";
defparam \reg_sel[1]~I .input_register_mode = "none";
defparam \reg_sel[1]~I .input_sync_reset = "none";
defparam \reg_sel[1]~I .oe_async_reset = "none";
defparam \reg_sel[1]~I .oe_power_up = "low";
defparam \reg_sel[1]~I .oe_register_mode = "none";
defparam \reg_sel[1]~I .oe_sync_reset = "none";
defparam \reg_sel[1]~I .operation_mode = "input";
defparam \reg_sel[1]~I .output_async_reset = "none";
defparam \reg_sel[1]~I .output_power_up = "low";
defparam \reg_sel[1]~I .output_register_mode = "none";
defparam \reg_sel[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X12_Y11_N2
cyclone_lcell \G_INSTRU_FETCH|start~I (
// Equation(s):
// \G_INSTRU_FETCH|start  = DFFEAS(VCC, !GLOBAL(\clk~combout ), GLOBAL(\reset~combout ), , , , , , )

	.clk(!\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\reset~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\G_INSTRU_FETCH|start ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \G_INSTRU_FETCH|start~I .lut_mask = "FFFF";
defparam \G_INSTRU_FETCH|start~I .operation_mode = "normal";
defparam \G_INSTRU_FETCH|start~I .output_mode = "reg_only";
defparam \G_INSTRU_FETCH|start~I .register_cascade_mode = "off";
defparam \G_INSTRU_FETCH|start~I .sum_lutc_input = "datac";
defparam \G_INSTRU_FETCH|start~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X12_Y11_N4
cyclone_lcell \G_INSTRU_FETCH|t1~I (
// Equation(s):
// \G_INSTRU_FETCH|t1  = DFFEAS(\G_INSTRU_FETCH|t3  # !\G_INSTRU_FETCH|start , GLOBAL(\clk~combout ), GLOBAL(\reset~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(\G_INSTRU_FETCH|start ),
	.datab(vcc),
	.datac(\G_INSTRU_FETCH|t3 ),
	.datad(vcc),
	.aclr(!\reset~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\G_INSTRU_FETCH|t1 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \G_INSTRU_FETCH|t1~I .lut_mask = "F5F5";
defparam \G_INSTRU_FETCH|t1~I .operation_mode = "normal";
defparam \G_INSTRU_FETCH|t1~I .output_mode = "reg_only";
defparam \G_INSTRU_FETCH|t1~I .register_cascade_mode = "off";