📄 ax88796.s
字号:
; unsigned int ax88796BeginPacketRetreive(void)
; {
.dbline 285
; unsigned char writePagePtr;
; unsigned char readPagePtr;
; unsigned char bnryPagePtr;
; unsigned char i;
;
; unsigned char pageheader[4];
; unsigned int rxlen;
;
; // check for and handle an overflow
; ax88796ProcessInterrupt();
xcall _ax88796ProcessInterrupt
.dbline 288
;
; // read CURR from page 1
; ax88796Write(CR,(PS0|RD2|START));
ldi R18,98
clr R16
xcall _ax88796Write
.dbline 289
; writePagePtr = ax88796Read(CURR);
ldi R16,7
xcall _ax88796Read
mov R10,R16
.dbline 291
; // read the boundary register from page 0
; ax88796Write(CR,(RD2|START));
ldi R18,34
clr R16
xcall _ax88796Write
.dbline 292
; bnryPagePtr = ax88796Read(BNRY);
ldi R16,3
xcall _ax88796Read
mov R20,R16
.dbline 295
;
; // first packet is at page bnryPtr+1
; readPagePtr = bnryPagePtr+1;
mov R22,R20
subi R22,255 ; addi 1
.dbline 296
; if(readPagePtr >= RXSTOP_INIT) readPagePtr = RXSTART_INIT;
cpi R22,96
brlo L32
.dbline 296
ldi R22,70
L32:
.dbline 299
;
; // return if there is no packet in the buffer
; if( readPagePtr == writePagePtr )
cp R22,R10
brne L34
.dbline 300
; {
.dbline 301
; return 0;
clr R16
clr R17
xjmp L31
L34:
.dbline 305
; }
;
; // clear the packet received interrupt flag
; ax88796Write(ISR, PRX);
ldi R18,1
ldi R16,7
xcall _ax88796Write
.dbline 309
;
; // if the boundary pointer is invalid,
; // reset the contents of the buffer and exit
; if( (bnryPagePtr < RXSTART_INIT) || (bnryPagePtr >= RXSTOP_INIT) )
cpi R20,70
brlo L38
cpi R20,96
brlo L36
L38:
.dbline 310
; {
.dbline 311
; ax88796Write(BNRY, RXSTART_INIT);
ldi R18,70
ldi R16,3
xcall _ax88796Write
.dbline 312
; ax88796Write(CR, (PS0|RD2|START));
ldi R18,98
clr R16
xcall _ax88796Write
.dbline 313
; ax88796Write(CURR, RXSTART_INIT+1);
ldi R18,71
ldi R16,7
xcall _ax88796Write
.dbline 314
; ax88796Write(CR, (RD2|START));
ldi R18,34
clr R16
xcall _ax88796Write
.dbline 315
; return 0;
clr R16
clr R17
xjmp L31
L36:
.dbline 319
; }
;
; // initiate DMA to transfer the RTL8019 packet header
; ax88796Write(RBCR0, 4);
ldi R18,4
ldi R16,10
xcall _ax88796Write
.dbline 320
; ax88796Write(RBCR1, 0);
clr R18
ldi R16,11
xcall _ax88796Write
.dbline 321
; ax88796Write(RSAR0, 0);
clr R18
ldi R16,8
xcall _ax88796Write
.dbline 322
; ax88796Write(RSAR1, readPagePtr);
mov R18,R22
ldi R16,9
xcall _ax88796Write
.dbline 323
; ax88796Write(CR, (RD0|START));
ldi R18,10
clr R16
xcall _ax88796Write
.dbline 324
; for(i=0;i<4;i++)
clr R20
xjmp L42
L39:
.dbline 325
ldi R16,16
xcall _ax88796Read
movw R24,R28
mov R30,R20
clr R31
add R30,R24
adc R31,R25
std z+0,R16
L40:
.dbline 324
inc R20
L42:
.dbline 324
cpi R20,4
brlo L39
.dbline 328
; pageheader[i] = ax88796Read(RDMAPORT);
;
; // end the DMA operation
; ax88796Write(CR, (RD2|START));
ldi R18,34
clr R16
xcall _ax88796Write
.dbline 329
; for(i = 0; i <= 20; i++)
clr R20
xjmp L46
L43:
.dbline 330
; if(ax88796Read(ISR) & RDC)
ldi R16,7
xcall _ax88796Read
sbrs R16,6
rjmp L47
.dbline 331
; break;
xjmp L45
L47:
L44:
.dbline 329
inc R20
L46:
.dbline 329
ldi R24,20
cp R24,R20
brsh L43
L45:
.dbline 332
; ax88796Write(ISR, RDC);
ldi R18,64
ldi R16,7
xcall _ax88796Write
.dbline 334
;
; rxlen = (pageheader[enetpacketLenH]<<8) + pageheader[enetpacketLenL];
ldd R2,y+2
ldd R3,y+3
mov R21,R3
mov R20,R2
.dbline 335
; nextPage = pageheader[nextblock_ptr] ;
ldd R2,y+1
sts _nextPage,R2
.dbline 337
;
; currentRetreiveAddress = (readPagePtr<<8) + 4;
ldi R24,4
mov R3,R22
mov R2,R24
sts _currentRetreiveAddress+1,R3
sts _currentRetreiveAddress,R2
.dbline 340
;
; // if the nextPage pointer is invalid, the packet is not ready yet - exit
; if( (nextPage >= RXSTOP_INIT) || (nextPage < RXSTART_INIT) )
lds R24,_nextPage
cpi R24,96
brsh L54
cpi R24,70
brsh L52
L54:
.dbline 341
; {
.dbline 342
; return 0;
clr R16
clr R17
xjmp L31
L52:
.dbline 345
; }
;
; return rxlen-4;
movw R16,R20
subi R16,4
sbci R17,0
.dbline -2
L31:
adiw R28,4
xcall pop_gset3
.dbline 0 ; func end
ret
.dbsym r rxlen 20 i
.dbsym r writePagePtr 10 c
.dbsym r bnryPagePtr 20 c
.dbsym r readPagePtr 22 c
.dbsym l pageheader 0 A[4:4]c
.dbsym r i 20 c
.dbend
.dbfunc e ax88796RetreivePacketData _ax88796RetreivePacketData fV
; i -> R22,R23
; length -> R20,R21
; localBuffer -> R10,R11
.even
_ax88796RetreivePacketData::
xcall push_gset3
movw R20,R18
movw R10,R16
.dbline -1
.dbline 350
; }
;
;
; void ax88796RetreivePacketData(unsigned char * localBuffer, unsigned int length)
; {
.dbline 354
; unsigned int i;
;
; // initiate DMA to transfer the data
; ax88796Write(RBCR0, (unsigned char)length);
mov R18,R20
ldi R16,10
xcall _ax88796Write
.dbline 355
; ax88796Write(RBCR1, (unsigned char)(length>>8));
movw R18,R20
mov R18,R19
clr R19
ldi R16,11
xcall _ax88796Write
.dbline 356
; ax88796Write(RSAR0, (unsigned char)currentRetreiveAddress);
lds R18,_currentRetreiveAddress
ldi R16,8
xcall _ax88796Write
.dbline 357
; ax88796Write(RSAR1, (unsigned char)(currentRetreiveAddress>>8));
lds R18,_currentRetreiveAddress
lds R19,_currentRetreiveAddress+1
mov R18,R19
clr R19
ldi R16,9
xcall _ax88796Write
.dbline 358
; ax88796Write(CR, (RD0|START));
ldi R18,10
clr R16
xcall _ax88796Write
.dbline 359
; for(i=0;i<length;i++)
clr R22
clr R23
xjmp L59
L56:
.dbline 360
ldi R16,16
xcall _ax88796Read
movw R30,R22
add R30,R10
adc R31,R11
std z+0,R16
L57:
.dbline 359
subi R22,255 ; offset = 1
sbci R23,255
L59:
.dbline 359
cp R22,R20
cpc R23,R21
brlo L56
.dbline 363
; localBuffer[i] = ax88796Read(RDMAPORT);
;
; // end the DMA operation
; ax88796Write(CR, (RD2|START));
ldi R18,34
clr R16
xcall _ax88796Write
.dbline 364
; for(i = 0; i <= 20; i++)
clr R22
clr R23
xjmp L63
L60:
.dbline 365
; if(ax88796Read(ISR) & RDC)
ldi R16,7
xcall _ax88796Read
sbrs R16,6
rjmp L64
.dbline 366
; break;
xjmp L62
L64:
L61:
.dbline 364
subi R22,255 ; offset = 1
sbci R23,255
L63:
.dbline 364
ldi R24,20
ldi R25,0
cp R24,R22
cpc R25,R23
brsh L60
L62:
.dbline 367
ldi R18,64
ldi R16,7
xcall _ax88796Write
.dbline 369
lds R2,_currentRetreiveAddress
lds R3,_currentRetreiveAddress+1
add R2,R20
adc R3,R21
sts _currentRetreiveAddress+1,R3
sts _currentRetreiveAddress,R2
.dbline 370
movw R24,R2
cpi R24,0
ldi R30,96
cpc R25,R30
brlo L66
.dbline 371
subi R24,0
sbci R25,26
sts _currentRetreiveAddress+1,R25
sts _currentRetreiveAddress,R24
L66:
.dbline -2
L55:
xcall pop_gset3
.dbline 0 ; func end
ret
.dbsym r i 22 i
.dbsym r length 20 i
.dbsym r localBuffer 10 pc
.dbend
.dbfunc e ax88796EndPacketRetreive _ax88796EndPacketRetreive fV
; bnryPagePtr -> R20
; i -> R20
.even
_ax88796EndPacketRetreive::
xcall push_gset1
.dbline -1
.dbline 377
; ax88796Write(ISR, RDC);
;
; currentRetreiveAddress += length;
; if( currentRetreiveAddress >= 0x6000 )
; currentRetreiveAddress -= (0x6000-0x4600) ;
; }
;
;
;
; void ax88796EndPacketRetreive(void)
; {
.dbline 382
; unsigned char i;
; unsigned char bnryPagePtr;
;
; // end the DMA operation
; ax88796Write(CR, (RD2|START));
ldi R18,34
clr R16
xcall _ax88796Write
.dbline 383
; for(i = 0; i <= 20; i++)
clr R20
xjmp L72
L69:
.dbline 384
; if(ax88796Read(ISR) & RDC)
ldi R16,7
xcall _ax88796Read
sbrs R16,6
rjmp L73
.dbline 385
; break;
xjmp L71
L73:
L70:
.dbline 383
inc R20
L72:
.dbline 383
ldi R24,20
cp R24,R20
brsh L69
L71:
.dbline 386
; ax88796Write(ISR, RDC);
ldi R18,64
ldi R16,7
xcall _ax88796Write
.dbline 390
;
; // set the boundary register to point
; // to the start of the next packet-1
; bnryPagePtr = nextPage-1;
lds R20,_nextPage
subi R20,1
.dbline 391
; if(bnryPagePtr < RXSTART_INIT) bnryPagePtr = RXSTOP_INIT-1;
cpi R20,70
brsh L75
.dbline 391
ldi R20,95
L75:
.dbline 393
;
; ax88796Write(BNRY, bnryPagePtr);
mov R18,R20
ldi R16,3
xcall _ax88796Write
.dbline -2
L68:
xcall pop_gset1
.dbline 0 ; func end
ret
.dbsym r bnryPagePtr 20 c
.dbsym r i 20 c
.dbend
.dbfunc e ax88796Overrun _ax88796Overrun fV
; resend -> R20
; cmdReg -> R22
.even
_ax88796Overrun::
xcall push_gset2
.dbline -1
.dbline 398
; }
;
;
; void ax88796Overrun(void)
; {
.dbline 402
; unsigned char cmdReg, resend;
;
; // check if we were transmitting something
; cmdReg = ax88796Read(CR);
clr R16
xcall _ax88796Read
mov R22,R16
.dbline 404
; // stop the interface
; ax88796Write(CR, (RD2|STOP));
ldi R18,33
clr R16
xcall _ax88796Write
.dbline 406
; // wait for timeout
; delay_ms(2);
ldi R16,2
xcall _delay_ms
.dbline 408
; // clear remote byte count registers
; ax88796Write(RBCR0, 0x00);
clr R18
ldi R16,10
xcall _ax88796Write
.dbline 409
; ax88796Write(RBCR1, 0x00);
clr R18
ldi R16,11
xcall _ax88796Write
.dbline 411
;
; if(!(cmdReg & TXP))
sbrc R22,2
rjmp L78
.dbline 412
; {
.dbline 413
; resend = 0;
clr R20
.dbline 414
; }
xjmp L79
L78:
.dbline 416
; else
; {
.dbline 417
; cmdReg = ax88796Read(ISR);
ldi R16,7
xcall _ax88796Read
mov R22,R16
.dbline 418
; if((cmdReg & PTX) || (cmdReg & TXE))
sbrc R16,1
rjmp L82
sbrs R16,2
rjmp L80
L82:
.dbline 419
; resend = 0;
clr R20
xjmp L81
L80:
.dbline 421
; else
; resend = 1;
ldi R20,1
L81:
.dbline 422
; }
L79:
.dbline 424
ldi R18,2
ldi R16,13
xcall _ax88796Write
.dbline 426
ldi R18,34
clr R16
xcall _ax88796Write
.dbline 428
ldi R18,70
ldi R16,3
xcall _ax88796Write
.dbline 430
ldi R18,98
clr R16
xcall _ax88796Write
.dbline 432
ldi R18,71
ldi R16,7
xcall _ax88796Write
.dbline 434
ldi R18,34
clr R16
xcall _ax88796Write
.dbline 436
ldi R18,16
ldi R16,7
xcall _ax88796Write
.dbline 438
clr R18
ldi R16,13
xcall _ax88796Write
.dbline 440
tst R20
breq L83
.dbline 441
ldi R18,38
clr R16
xcall _ax88796Write
L83:
.dbline -2
L77:
xcall pop_gset2
.dbline 0 ; func end
ret
.dbsym r resend 20 c
.dbsym r cmdReg 22 c
.dbend
.dbfunc e ax88796WriteMii _ax88796WriteMii fV
; mask16 -> R20,R21
; mask8 -> R22
; i -> R10,R11
; mii_data -> R12,R13
; regad -> R14
; phyad -> y+10
.even
_ax88796WriteMii::
xcall push_arg4
xcall push_gset5
mov R14,R18
ldd R12,y+14
ldd R13,y+15
.dbline -1
.dbline 484
; // switch to loopback mode
; ax88796Write(TCR, LB0);
; // start the interface
; ax88796Write(CR, (RD2|START));
; // set boundary
; ax88796Write(BNRY, RXSTART_INIT);
; // go to page 1
; ax88796Write(CR, (PS0|RD2|START));
; // set current page register
; ax88796Write(CURR, RXSTART_INIT+1);
; // go to page 0
; ax88796Write(CR, (RD2|START));
; // clear the overflow int
; ax88796Write(ISR, OVW);
; // switch to normal (non-loopback mode)
; ax88796Write(TCR, TCR_INIT);
;
; if(resend)
; ax88796Write(CR, (RD2|TXP|START));
;
; //ax88796Write(ISR, 0xFF);
; }
;
; #define set_mdc ax88796Write(MEMR,ax88796Read(MEMR)|0x01);
; #define clr_mdc ax88796Write(MEMR,ax88796Read(MEMR)&0xFE);
;
; #define mii_clk set_mdc; clr_mdc;
;
; #define set_mdir ax88796Write(MEMR,ax88796Read(MEMR)|0x02);
; #define clr_mdir ax88796Write(MEMR,ax88796Read(MEMR)&0xFD);
;
; #define set_mdo ax88796Write(MEMR,ax88796Read(MEMR)|0x08)
; #define clr_mdo ax88796Write(MEMR,ax88796Read(MEMR)&0xF7)
;
; #define mii_write clr_mdo; \
; mii_clk; \
; set_mdo; \
; mii_clk; \
; clr_mdo; \
; mii_clk; \
; set_mdo; \
; mii_clk;
;
; #define mii_read clr_mdo; \
; mii_clk; \
; set_mdo; \
; mii_clk; \
; set_mdo; \
; mii_clk; \
; clr_mdo; \
; mii_clk;
;
; #define mii_r_ta mii_clk; \
;
;
; #define mii_w_ta set_mdo; \
; mii_clk; \
; clr_mdo; \
; mii_clk;
;
; void ax88796WriteMii(unsigned char phyad,unsigned char regad,unsigned int mii_data)
; {
.dbline 488
; unsigned char mask8;
; unsigned int i,mask16;
;
; mii_write;
ldi R16,20
xcall _ax88796Read
mov R18,R16
andi R18,247
ldi R16,20
xcall _ax88796Write
.dbline 488
ldi R16,20
xcall _ax88796Read
mov R18,R16
ori R18,1
ldi R16,20
xcall _ax88796Write
.dbline 488
.dbline 488
ldi R16,20
xcall _ax88796Read
mov R18,R16
andi R18,254
ldi R16,20
xcall _ax88796Write
.dbline 488
.dbline 488
.dbline 488
ldi R16,20
xcall _ax88796Read
mov R18,R16
ori R18,8
ldi R16,20
xcall _ax88796Write
.dbline 488
ldi R16,20
xcall _ax88796Read
mov R18,R16
ori R18,1
ldi R16,20
xcall _ax88796Write
.dbline 488
.dbline 488
ldi R16,20
xcall _ax88796Read
mov R18,R16
andi R18,254
ldi R16,20
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -