📄 ax88796.lis
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00B2 0BE0 ldi R16,11
00B4 A5DF xcall _ax88796Write
00B6 .dbline 154
00B6 ; ax88796Write(IMR,0x00);
00B6 2227 clr R18
00B8 0FE0 ldi R16,15
00BA A2DF xcall _ax88796Write
00BC .dbline 155
00BC ; ax88796Write(ISR,0xFF);
00BC 2FEF ldi R18,255
00BE 07E0 ldi R16,7
00C0 9FDF xcall _ax88796Write
00C2 .dbline 156
00C2 ; ax88796Write(RCR,0x20);
00C2 20E2 ldi R18,32
00C4 0CE0 ldi R16,12
00C6 9CDF xcall _ax88796Write
00C8 .dbline 157
00C8 ; ax88796Write(BNRY,RXSTART_INIT);
00C8 26E4 ldi R18,70
00CA 03E0 ldi R16,3
00CC 99DF xcall _ax88796Write
00CE .dbline 158
00CE ; ax88796Write(PSTART,RXSTART_INIT);
00CE 26E4 ldi R18,70
00D0 01E0 ldi R16,1
00D2 96DF xcall _ax88796Write
00D4 .dbline 159
00D4 ; ax88796Write(PSTOP,RXSTOP_INIT);
00D4 20E6 ldi R18,96
00D6 02E0 ldi R16,2
00D8 93DF xcall _ax88796Write
00DA .dbline 162
00DA ;
00DA ; // switch to page 1
00DA ; ax88796Write(CR,(PS0|RD2|STOP));
00DA 21E6 ldi R18,97
00DC 0027 clr R16
00DE 90DF xcall _ax88796Write
00E0 .dbline 164
00E0 ; // write mac address
00E0 ; ax88796Write(PAR0+0, MYMAC_0);
00E0 20E3 ldi R18,48
00E2 01E0 ldi R16,1
00E4 8DDF xcall _ax88796Write
00E6 .dbline 165
00E6 ; ax88796Write(PAR0+1, MYMAC_1);
00E6 26E4 ldi R18,70
00E8 02E0 ldi R16,2
00EA 8ADF xcall _ax88796Write
00EC .dbline 166
00EC ; ax88796Write(PAR0+2, MYMAC_2);
00EC 26E4 ldi R18,70
00EE 03E0 ldi R16,3
00F0 87DF xcall _ax88796Write
00F2 .dbline 167
00F2 ; ax88796Write(PAR0+3, MYMAC_3);
00F2 29E4 ldi R18,73
00F4 04E0 ldi R16,4
00F6 84DF xcall _ax88796Write
00F8 .dbline 168
00F8 ; ax88796Write(PAR0+4, MYMAC_4);
00F8 23E4 ldi R18,67
00FA 05E0 ldi R16,5
00FC 81DF xcall _ax88796Write
00FE .dbline 169
00FE ; ax88796Write(PAR0+5, MYMAC_5);
00FE 25E4 ldi R18,69
0100 06E0 ldi R16,6
0102 7EDF xcall _ax88796Write
0104 .dbline 171
0104 ; // set start point
0104 ; ax88796Write(CURR,RXSTART_INIT+1);
0104 27E4 ldi R18,71
0106 07E0 ldi R16,7
0108 7BDF xcall _ax88796Write
010A .dbline 173
010A ;
010A ; ax88796Write(CR,(RD2|START));
010A 22E2 ldi R18,34
010C 0027 clr R16
010E 78DF xcall _ax88796Write
0110 .dbline 174
0110 ; ax88796Write(RCR,RCR_INIT);
0110 24E4 ldi R18,68
0112 0CE0 ldi R16,12
0114 75DF xcall _ax88796Write
0116 .dbline 176
0116 ;
0116 ; if(ax88796Read(GPI) & I_SPD) // check PHY speed setting
0116 07E1 ldi R16,23
0118 81DF xcall _ax88796Read
011A 02FF sbrs R16,2
011C 02C0 rjmp L16
011E .dbline 177
011E ; tcrFduFlag = FDU; // if 100base, do full duplex
011E 40E8 ldi R20,128
0120 01C0 xjmp L17
0122 L16:
0122 .dbline 179
0122 ; else
0122 ; tcrFduFlag = 0; // if 10base, do half duplex
0122 4427 clr R20
0124 L17:
0124 .dbline 181
0124 ;
0124 ; ax88796Write(TCR,(tcrFduFlag|TCR_INIT));
0124 242F mov R18,R20
0126 0DE0 ldi R16,13
0128 6BDF xcall _ax88796Write
012A .dbline 183
012A ;
012A ; ax88796Write(GPOC,MPSEL); // select media interface
012A 20E1 ldi R18,16
012C 07E1 ldi R16,23
012E 68DF xcall _ax88796Write
0130 .dbline 185
0130 ;
0130 ; ax88796Write(TPSR,TXSTART_INIT);
0130 20E4 ldi R18,64
0132 04E0 ldi R16,4
0134 65DF xcall _ax88796Write
0136 .dbline 187
0136 ;
0136 ; ax88796Write(CR,(RD2|STOP));
0136 21E2 ldi R18,33
0138 0027 clr R16
013A 62DF xcall _ax88796Write
013C .dbline 188
013C ; ax88796Write(DCR,DCR_INIT);
013C 2227 clr R18
013E 0EE0 ldi R16,14
0140 5FDF xcall _ax88796Write
0142 .dbline 189
0142 ; ax88796Write(CR,(RD2|START));
0142 22E2 ldi R18,34
0144 0027 clr R16
0146 5CDF xcall _ax88796Write
0148 .dbline 190
0148 ; ax88796Write(ISR,0xFF);
0148 2FEF ldi R18,255
014A 07E0 ldi R16,7
014C 59DF xcall _ax88796Write
014E .dbline 191
014E ; ax88796Write(IMR,IMR_INIT);
014E 21E1 ldi R18,17
0150 0FE0 ldi R16,15
0152 56DF xcall _ax88796Write
0154 .dbline 192
0154 ; ax88796Write(TCR,(tcrFduFlag|TCR_INIT));
0154 242F mov R18,R20
0156 0DE0 ldi R16,13
0158 53DF xcall _ax88796Write
015A .dbline -2
015A L9:
015A 2296 adiw R28,2
015C 0E940000 xcall pop_gset2
0160 .dbline 0 ; func end
0160 0895 ret
0162 .dbsym r tcrFduFlag 20 c
0162 .dbsym r delaycount 22 c
0162 .dbend
0162 .dbfunc e ax88796SetupPorts _ax88796SetupPorts fV
.even
0162 _ax88796SetupPorts::
0162 .dbline -1
0162 .dbline 198
0162 ; }
0162 ;
0162 ;
0162 ;
0162 ; void ax88796SetupPorts(void)
0162 ; {
0162 .dbline 201
0162 ; #if NIC_CONNECTION == GENERAL_IO
0162 ; // set address port to output
0162 ; AX88796_ADDRESS_DDR = AX88796_ADDRESS_MASK;
0162 8FE1 ldi R24,31
0164 84BB out 0x14,R24
0166 .dbline 204
0166 ;
0166 ; // set data port to input with pull-ups
0166 ; AX88796_DATA_DDR = 0x00;
0166 2224 clr R2
0168 2ABA out 0x1a,R2
016A .dbline 205
016A ; AX88796_DATA_PORT = 0xFF;
016A 8FEF ldi R24,255
016C 8BBB out 0x1b,R24
016E .dbline 208
016E ;
016E ; // initialize the control port read and write pins to de-asserted
016E ; AX88796_CONTROL_PORT |= _BV(AX88796_CONTROL_READPIN);
016E AD9A sbi 0x15,5
0170 .dbline 209
0170 ; AX88796_CONTROL_PORT |= _BV(AX88796_CONTROL_WRITEPIN);
0170 AE9A sbi 0x15,6
0172 .dbline 211
0172 ; // set the read and write pins to output
0172 ; AX88796_CONTROL_DDR |= _BV(AX88796_CONTROL_READPIN);
0172 A59A sbi 0x14,5
0174 .dbline 212
0174 ; AX88796_CONTROL_DDR |= _BV(AX88796_CONTROL_WRITEPIN);
0174 A69A sbi 0x14,6
0176 .dbline 219
0176 ;
0176 ; #else
0176 ; // enable external SRAM interface - no wait states
0176 ; MCUCR |= _BV(SRE);
0176 ; #endif
0176 ; // set reset pin to output
0176 ; AX88796_RESET_DDR |= _BV(AX88796_RESET_PIN);
0176 8A9A sbi 0x11,2
0178 .dbline -2
0178 L18:
0178 .dbline 0 ; func end
0178 0895 ret
017A .dbend
017A .dbfunc e ax88796BeginPacketSend _ax88796BeginPacketSend fV
017A ; sendPacketLength -> R20,R21
017A ; packetLength -> R22,R23
.even
017A _ax88796BeginPacketSend::
017A 0E940000 xcall push_gset3
017E B801 movw R22,R16
0180 .dbline -1
0180 .dbline 224
0180 ; }
0180 ;
0180 ;
0180 ; void ax88796BeginPacketSend(unsigned int packetLength)
0180 ; {
0180 .dbline 226
0180 ; unsigned int sendPacketLength;
0180 ; sendPacketLength = (packetLength>=ETHERNET_MIN_PACKET_LENGTH) ?
0180 6C33 cpi R22,60
0182 E0E0 ldi R30,0
0184 7E07 cpc R23,R30
0186 10F0 brlo L20
0188 5B01 movw R10,R22
018A 03C0 xjmp L21
018C L20:
018C 8CE3 ldi R24,60
018E 90E0 ldi R25,0
0190 5C01 movw R10,R24
0192 L21:
0192 A501 movw R20,R10
0194 .dbline 230
0194 ; packetLength : ETHERNET_MIN_PACKET_LENGTH ;
0194 ;
0194 ; //start the NIC
0194 ; ax88796Write(CR,0x22);
0194 22E2 ldi R18,34
0196 0027 clr R16
0198 33DF xcall _ax88796Write
019A L22:
019A .dbline 233
019A L23:
019A .dbline 233
019A ;
019A ; // still transmitting a packet - wait for it to finish
019A ; while( ax88796Read(CR) & 0x04 );
019A 0027 clr R16
019C 3FDF xcall _ax88796Read
019E 02FD sbrc R16,2
01A0 FCCF rjmp L22
01A2 .dbline 236
01A2 ;
01A2 ; //load beginning page for transmit buffer
01A2 ; ax88796Write(TPSR,TXSTART_INIT);
01A2 20E4 ldi R18,64
01A4 04E0 ldi R16,4
01A6 2CDF xcall _ax88796Write
01A8 .dbline 239
01A8 ;
01A8 ; //set start address for remote DMA operation
01A8 ; ax88796Write(RSAR0,0x00);
01A8 2227 clr R18
01AA 08E0 ldi R16,8
01AC 29DF xcall _ax88796Write
01AE .dbline 240
01AE ; ax88796Write(RSAR1,0x40);
01AE 20E4 ldi R18,64
01B0 09E0 ldi R16,9
01B2 26DF xcall _ax88796Write
01B4 .dbline 243
01B4 ;
01B4 ; //clear the packet stored interrupt
01B4 ; ax88796Write(ISR, PTX);
01B4 22E0 ldi R18,2
01B6 07E0 ldi R16,7
01B8 23DF xcall _ax88796Write
01BA .dbline 246
01BA ;
01BA ; //load data byte count for remote DMA
01BA ; ax88796Write(RBCR0, (unsigned char)(packetLength));
01BA 262F mov R18,R22
01BC 0AE0 ldi R16,10
01BE 20DF xcall _ax88796Write
01C0 .dbline 247
01C0 ; ax88796Write(RBCR1, (unsigned char)(packetLength>>8));
01C0 9B01 movw R18,R22
01C2 232F mov R18,R19
01C4 3327 clr R19
01C6 0BE0 ldi R16,11
01C8 1BDF xcall _ax88796Write
01CA .dbline 249
01CA ;
01CA ; ax88796Write(TBCR0, (unsigned char)(sendPacketLength));
01CA 242F mov R18,R20
01CC 05E0 ldi R16,5
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