📄 ax88796.lis
字号:
.module ax88796.c
.area text(rom, con, rel)
0000 .dbfile C:\DOCUME~1\yehaoran\桌面\AVRuIP\ax88796.c
0000 .dbfunc e ax88796Write _ax88796Write fV
0000 ; data -> R18
0000 ; address -> R16
.even
0000 _ax88796Write::
0000 .dbline -1
0000 .dbline 66
0000 ; /*****************************************************************************
0000 ; * modified by Louis Beaudoin for uIP-AVR port - November 16, 2003
0000 ; * www.embedded-creations.com
0000 ; *
0000 ; * Removed: The debugging calls to the Procyon AVRLIB UART functions and the
0000 ; * register dump function was removed
0000 ; *
0000 ; * Modified:
0000 ; * The ax88796Write and Read functions/macros were changed to support
0000 ; * three methods of communcating with the NIC
0000 ; * Interfacing with the AVR ports changed from sbi/cbi/etc functions
0000 ; * to direct port names
0000 ; *****************************************************************************/
0000 ;
0000 ; //*****************************************************************************
0000 ; //
0000 ; // File Name : 'ax88796.c'
0000 ; // Title : ASIX 88796 L Ethernet Interface Driver
0000 ; // Author : Pascal Stang
0000 ; // Created : 10/22/2002
0000 ; // Revised : 10/26/2002
0000 ; // Version : 0.1
0000 ; // Target MCU : Atmel AVR series
0000 ; // Editor Tabs : 4
0000 ; //
0000 ; // Description : This include file is designed to contain items useful to all
0000 ; // code files and projects.
0000 ; //
0000 ; // Based in part on code by Louis Beaudoin (www.embedded-creations.com)
0000 ; //
0000 ; // This code is distributed under the GNU Public License
0000 ; // which can be found at http://www.gnu.org/licenses/gpl.txt
0000 ; //
0000 ; //*****************************************************************************
0000 ;
0000 ; #include "ax88796.h"
0000 ;
0000 ; // pointers to locations in the ax88796 receive buffer
0000 ; static unsigned char nextPage;
0000 ; static unsigned int currentRetreiveAddress;
0000 ;
0000 ; // offsets into ax88796 ethernet packet header
0000 ; #define enetpacketstatus 0x00
0000 ; #define nextblock_ptr 0x01
0000 ; #define enetpacketLenL 0x02
0000 ; #define enetpacketLenH 0x03
0000 ;
0000 ;
0000 ;
0000 ; #if NIC_CONNECTION == MEMORY_MAPPED_HIGHADDR
0000 ; #define ax88796Write(AX88796_REG,AX88796_DATA) do{ *(volatile unsigned char *) \
0000 ; (MEMORY_MAPPED_AX88796_OFFSET \
0000 ; + (((unsigned char)(AX88796_REG)) << 8)) = \
0000 ; (unsigned char)(AX88796_DATA); } while(0)
0000 ; #endif
0000 ;
0000 ; #if NIC_CONNECTION == MEMORY_MAPPED
0000 ; #define ax88796Write(AX88796_REG,AX88796_DATA) do{ *(volatile unsigned char *) \
0000 ; (MEMORY_MAPPED_AX88796_OFFSET \
0000 ; + (unsigned char)(AX88796_REG)) = \
0000 ; (unsigned char)(AX88796_DATA); } while(0)
0000 ; #endif
0000 ;
0000 ; #if NIC_CONNECTION == GENERAL_IO
0000 ; void ax88796Write(u08 address, u08 data)
0000 ; {
0000 .dbline 68
0000 ; // assert the address, leaving the non-address pins intact
0000 ; address |= (AX88796_ADDRESS_PORT & ~AX88796_ADDRESS_MASK);
0000 85B3 in R24,0x15
0002 807E andi R24,224
0004 082B or R16,R24
0006 .dbline 69
0006 ; AX88796_ADDRESS_PORT = address;
0006 05BB out 0x15,R16
0008 .dbline 72
0008 ;
0008 ; // set data bus as output and place data on bus
0008 ; AX88796_DATA_DDR = 0xFF;
0008 8FEF ldi R24,255
000A 8ABB out 0x1a,R24
000C .dbline 73
000C ; AX88796_DATA_PORT = data;
000C 2BBB out 0x1b,R18
000E .dbline 76
000E ;
000E ; // clock write pin
000E ; AX88796_CONTROL_PORT &= ~_BV(AX88796_CONTROL_WRITEPIN);
000E AE98 cbi 0x15,6
0010 .dbline 77
0010 ; nop();
0010 0000 nop
0012 .dbline 78
0012 ; AX88796_CONTROL_PORT |= _BV(AX88796_CONTROL_WRITEPIN);
0012 AE9A sbi 0x15,6
0014 .dbline 81
0014 ;
0014 ; // set data bus back to input with pullups enabled
0014 ; AX88796_DATA_DDR = 0x00;
0014 2224 clr R2
0016 2ABA out 0x1a,R2
0018 .dbline 82
0018 ; AX88796_DATA_PORT = 0xFF;
0018 8BBB out 0x1b,R24
001A .dbline -2
001A L7:
001A .dbline 0 ; func end
001A 0895 ret
001C .dbsym r data 18 c
001C .dbsym r address 16 c
001C .dbend
001C .dbfunc e ax88796Read _ax88796Read fc
001C ; byte -> R20
001C ; address -> R16
.even
001C _ax88796Read::
001C 0E940000 xcall push_gset1
0020 .dbline -1
0020 .dbline 102
0020 ; }
0020 ; #endif
0020 ;
0020 ; #if NIC_CONNECTION == MEMORY_MAPPED_HIGHADDR
0020 ;
0020 ; #define ax88796Read(AX88796_ADDRESS) (*(volatile unsigned char *) \
0020 ; (MEMORY_MAPPED_AX88796_OFFSET \
0020 ; + (((unsigned char)(AX88796_ADDRESS)) << 8)) )
0020 ; #endif
0020 ;
0020 ; #if NIC_CONNECTION == MEMORY_MAPPED
0020 ; #define ax88796Read(AX88796_ADDRESS) (*(volatile unsigned char *) \
0020 ; (MEMORY_MAPPED_AX88796_OFFSET \
0020 ; + (unsigned char)(AX88796_ADDRESS)) )
0020 ; #endif
0020 ;
0020 ; #if NIC_CONNECTION == GENERAL_IO
0020 ;
0020 ; u08 ax88796Read(u08 address)
0020 ; {
0020 .dbline 106
0020 ; u08 byte;
0020 ;
0020 ; // assert the address, leaving the non-address pins intact
0020 ; address |= (AX88796_ADDRESS_PORT & ~AX88796_ADDRESS_MASK);
0020 85B3 in R24,0x15
0022 807E andi R24,224
0024 082B or R16,R24
0026 .dbline 107
0026 ; AX88796_ADDRESS_PORT = address;
0026 05BB out 0x15,R16
0028 .dbline 110
0028 ;
0028 ; // assert read
0028 ; AX88796_CONTROL_PORT &= ~_BV(AX88796_CONTROL_READPIN);
0028 AD98 cbi 0x15,5
002A .dbline 111
002A ; nop();
002A 0000 nop
002C .dbline 114
002C ;
002C ; // read in the data
002C ; byte = AX88796_DATA_PIN;
002C 49B3 in R20,0x19
002E .dbline 115
002E ; nop();
002E 0000 nop
0030 .dbline 118
0030 ;
0030 ; // negate read
0030 ; AX88796_CONTROL_PORT |= _BV(AX88796_CONTROL_READPIN);
0030 AD9A sbi 0x15,5
0032 .dbline 120
0032 ;
0032 ; return byte;
0032 042F mov R16,R20
0034 .dbline -2
0034 L8:
0034 0E940000 xcall pop_gset1
0038 .dbline 0 ; func end
0038 0895 ret
003A .dbsym r byte 20 c
003A .dbsym r address 16 c
003A .dbend
003A .dbfunc e ax88796Init _ax88796Init fV
003A ; tcrFduFlag -> R20
003A ; delaycount -> R22
.even
003A _ax88796Init::
003A 0E940000 xcall push_gset2
003E 2297 sbiw R28,2
0040 .dbline -1
0040 .dbline 126
0040 ; }
0040 ; #endif
0040 ;
0040 ;
0040 ; void ax88796Init(void)
0040 ; {
0040 .dbline 127
0040 ; unsigned char delaycount=10;
0040 6AE0 ldi R22,10
0042 .dbline 129
0042 ; unsigned char tcrFduFlag;
0042 ; ax88796SetupPorts();
0042 8FD0 xcall _ax88796SetupPorts
0044 .dbline 132
0044 ;
0044 ; // do a hard reset
0044 ; AX88796_RESET_PORT |= _BV(AX88796_RESET_PIN);
0044 929A sbi 0x12,2
0046 .dbline 133
0046 ; delay_ms(10);
0046 0AE0 ldi R16,10
0048 0E940000 xcall _delay_ms
004C .dbline 134
004C ; AX88796_RESET_PORT &= ~_BV(AX88796_RESET_PIN);
004C 9298 cbi 0x12,2
004E .dbline 137
004E ;
004E ; // do soft reset
004E ; ax88796Write(ISR, ax88796Read(ISR));
004E 07E0 ldi R16,7
0050 E5DF xcall _ax88796Read
0052 202F mov R18,R16
0054 07E0 ldi R16,7
0056 D4DF xcall _ax88796Write
0058 .dbline 138
0058 ; delay_ms(50);
0058 02E3 ldi R16,50
005A 0E940000 xcall _delay_ms
005E .dbline 141
005E ;
005E ; // wait for PHY to come out of reset
005E ; ax88796Read(RSTPORT);
005E 0FE1 ldi R16,31
0060 DDDF xcall _ax88796Read
0062 L10:
0062 .dbline 142
0062 L11:
0062 .dbline 142
0062 ; while(ax88796Read(TR) & RST_B);
0062 05E1 ldi R16,21
0064 DBDF xcall _ax88796Read
0066 01FD sbrc R16,1
0068 FCCF rjmp L10
006A .dbline 144
006A ;
006A ; ax88796WriteMii(0x10,0x00,0x0800);
006A 80E0 ldi R24,2048
006C 98E0 ldi R25,8
006E 9983 std y+1,R25
0070 8883 std y+0,R24
0072 2227 clr R18
0074 00E1 ldi R16,16
0076 02D2 xcall _ax88796WriteMii
0078 03C0 xjmp L14
007A L13:
007A .dbline 146
007A 0FEF ldi R16,255
007C 0E940000 xcall _delay_ms
0080 L14:
0080 .dbline 145
0080 ; while(delaycount--)
0080 262E mov R2,R22
0082 3324 clr R3
0084 6150 subi R22,1
0086 2220 tst R2
0088 C1F7 brne L13
008A .dbline 147
008A ; delay_ms(255);
008A ; ax88796WriteMii(0x10,0x00,0x1200);
008A 80E0 ldi R24,4608
008C 92E1 ldi R25,18
008E 9983 std y+1,R25
0090 8883 std y+0,R24
0092 2227 clr R18
0094 00E1 ldi R16,16
0096 F2D1 xcall _ax88796WriteMii
0098 .dbline 149
0098 ;
0098 ; ax88796Write(CR,(RD2|STOP)); // stop the NIC, abort DMA, page 0
0098 21E2 ldi R18,33
009A 0027 clr R16
009C B1DF xcall _ax88796Write
009E .dbline 150
009E ; delay_ms(5); // make sure nothing is coming in or going out
009E 05E0 ldi R16,5
00A0 0E940000 xcall _delay_ms
00A4 .dbline 151
00A4 ; ax88796Write(DCR,DCR_INIT);
00A4 2227 clr R18
00A6 0EE0 ldi R16,14
00A8 ABDF xcall _ax88796Write
00AA .dbline 152
00AA ; ax88796Write(RBCR0,0x00);
00AA 2227 clr R18
00AC 0AE0 ldi R16,10
00AE A8DF xcall _ax88796Write
00B0 .dbline 153
00B0 ; ax88796Write(RBCR1,0x00);
00B0 2227 clr R18
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