cpu_sys.ucf

jam CPU模拟器的设计与实现.其中包含设计文档

#Timing (20MHz internal -  80MHz external)
NET clockc_c(1) PERIOD = 50.000;
NET clk PERIOD = 12.500;

#Pins
net clk loc=al16;
net k_en loc=ad30;
net k_in loc=aa30;
net k_in PULLDOWN;
net dm_write loc=d1; 
net dm_oe loc=d2; 
net dm_cs(0) loc=e1; 
net dm_cs(1) loc=e3; 
net dm_cs(2) loc=f2; 
net dm_cs(3) loc=f3; 
net dm_cs(4) loc=g2; 
net dm_cs(5) loc=h2; 
net dm_cs(6) loc=u1; 
net dm_cs(7) loc=u2; 
#net d_c(11) loc=aa2; 
#net d_c(13) loc=ac3; 
#net d_c(14) loc=ad1; 
#net dm_datais loc=ad2; 
net dm_adr(0) loc=c2; 
net dm_adr(1) loc=k4; 
net dm_adr(2) loc=k2; 
net dm_adr(3) loc=p4; 
net dm_adr(4) loc=v4; 
net dm_adr(5) loc=ab1; 
net dm_adr(6) loc=ab3; 
net dm_adr(7) loc=ag4; 
net dm_adr(8) loc=t3; 
net dm_adr(9) loc=r1; 
net dm_adr(10) loc=r2; 
net dm_adr(11) loc=r4; 
net dm_adr(12) loc=p2; 
net dm_adr(13) loc=p3; 
net dm_adr(14) loc=n3; 
net dm_adr(15) loc=n4; 
net dm_adr(16) loc=m1; 
#net dm_adr(17) loc=m2; 
#net dm_adr(18) loc=m4; 
#net dm_adr(19) loc=l2; 
net dm_data(0) loc=ae2; 
net dm_data(1) loc=ae3; 
net dm_data(2) loc=af2; 
net dm_data(3) loc=ag1; 
net dm_data(4) loc=ag2; 
net dm_data(5) loc=ag3; 
net dm_data(6) loc=ah1; 
net dm_data(7) loc=ah2; 
net dm_data(8) loc=ak3; 
net dm_data(9) loc=ak4; 
net dm_data(10) loc=aj4; 
net dm_data(11) loc=al5; 
net dm_data(12) loc=ak5; 
net dm_data(13) loc=aj5; 
net dm_data(14) loc=al6; 
net dm_data(15) loc=ak6; 
net dm_data(16) loc=aj6; 
net dm_data(17) loc=ak7; 
net dm_data(18) loc=ah7; 
net dm_data(19) loc=aj8; 
net dm_data(20) loc=ak9; 
net dm_data(21) loc=aj9; 
net dm_data(22) loc=al10; 
net dm_data(23) loc=ak10; 
net dm_data(24) loc=ah10; 
net dm_data(25) loc=ak11; 
net dm_data(26) loc=aj11; 
net dm_data(27) loc=al12; 
net dm_data(28) loc=ak12; 
net dm_data(29) loc=aj13; 
net dm_data(30) loc=ah13; 
net dm_data(31) loc=ak14; 
net dm_data(32) loc=aj14; 
net dm_data(33) loc=al15; 
net dm_data(34) loc=aj15; 
net dm_data(35) loc=ah15; 
net dm_data(36) loc=al17; 
net dm_data(37) loc=ak17; 
net dm_data(38) loc=ah17; 
net dm_data(39) loc=ak18; 
net dm_data(40) loc=ah18; 
net dm_data(41) loc=al19; 
net dm_data(42) loc=aj19; 
net dm_data(43) loc=al20; 
net dm_data(44) loc=ak20; 
net dm_data(45) loc=aj20; 
net dm_data(46) loc=ak21; 
net dm_data(47) loc=aj21; 
net dm_data(48) loc=al22; 
net dm_data(49) loc=aj22; 
net dm_data(50) loc=ah22; 
net dm_data(51) loc=aj23; 
net dm_data(52) loc=ah23; 
net dm_data(53) loc=ak24; 
net dm_data(54) loc=aj24; 
net dm_data(55) loc=ak25; 
net dm_data(56) loc=ah25; 
net dm_data(57) loc=al26; 
net dm_data(58) loc=ak26; 
net dm_data(59) loc=aj26; 
net dm_data(60) loc=al27; 
net dm_data(61) loc=aj27; 
net dm_data(62) loc=al28; 
net dm_data(63) loc=ak28; 
net im_write loc=l30; 
net im_oe loc=l29; 
net im_cs(0) loc=k31; 
net im_cs(1) loc=k30; 
net im_cs(2) loc=j30; 
net im_cs(3) loc=j29; 
net im_cs(4) loc=h31; 
net im_cs(5) loc=h30; 
net im_cs(6) loc=y31; 
net im_cs(7) loc=y30; 
#net im_datais loc=ag31; 
net im_adr(0) loc=w30; 
net im_adr(1) loc=w29; 
net im_adr(2) loc=w28; 
net im_adr(3) loc=v30; 
net im_adr(4) loc=v29; 
net im_adr(5) loc=u31; 
net im_adr(6) loc=u30; 
net im_adr(7) loc=u29; 
net im_adr(8) loc=t31; 
net im_adr(9) loc=t30; 
net im_adr(10) loc=r30; 
net im_adr(11) loc=r29; 
net im_adr(12) loc=r28; 
net im_adr(13) loc=p30; 
net im_adr(14) loc=p29; 
net im_adr(15) loc=p28; 
net im_adr(16) loc=n31; 
#net im_adr(17) loc=n28; 
#net im_adr(18) loc=m31; 
#net im_adr(19) loc=m30; 
net im_data(0) loc=g30; 
net im_data(1) loc=g29; 
net im_data(2) loc=f29; 
net im_data(3) loc=e31; 
net im_data(4) loc=e30; 
net im_data(5) loc=e29; 
net im_data(6) loc=d31; 
net im_data(7) loc=d30; 
net im_data(8) loc=c30; 
net im_data(9) loc=B29; 
net im_data(10) loc=a28; 
net im_data(11) loc=b28; 
net im_data(12) loc=c28; 
net im_data(13) loc=a27; 
net im_data(14) loc=b27; 
net im_data(15) loc=c27; 
net im_data(16) loc=a26; 
net im_data(17) loc=c26; 
net im_data(18) loc=b25; 
net im_data(19) loc=c25; 
net im_data(20) loc=a24; 
net im_data(21) loc=b24; 
net im_data(22) loc=c23; 
net im_data(23) loc=d23; 
net im_data(24) loc=a22; 
net im_data(25) loc=b22; 
net im_data(26) loc=c22; 
net im_data(27) loc=c21; 
net im_data(28) loc=a20; 
net im_data(29) loc=b20; 
net im_data(30) loc=c20; 
net im_data(31) loc=a19; 
net im_data(32) loc=d19; 
net im_data(33) loc=b18; 
net im_data(34) loc=b17; 
net im_data(35) loc=c17;
net im_data(36) loc=b16; 
net im_data(37) loc=c16;
net im_data(38) loc=a15;
net im_data(39) loc=c15; 
net im_data(40) loc=b14; 
net im_data(41) loc=d14; 
net im_data(42) loc=b13; 
net im_data(43) loc=c13; 
net im_data(44) loc=a12; 
net im_data(45) loc=c12; 
net im_data(46) loc=d12; 
net im_data(47) loc=b11; 
net im_data(48) loc=c11; 
net im_data(49) loc=b10; 
net im_data(50) loc=b9; 
net im_data(51) loc=c9;
net im_data(52) loc=d9;
net im_data(53) loc=a8;
net im_data(54) loc=b8; 
net im_data(55) loc=c8; 
net im_data(56) loc=d7; 
net im_data(57) loc=a6; 
net im_data(58) loc=b6; 
net im_data(59) loc=d6; 
net im_data(60) loc=a5; 
net im_data(61) loc=b5; 
net im_data(62) loc=c5; 
net im_data(63) loc=a4;