⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 insnsa.c

📁 nasm早期的源代码,比较简单是学习汇编和编译原理的好例子
💻 C
📖 第 1 页 / 共 5 页
字号:
🔍
12345 

static const struct itemplate instrux_FLDZ[] = {
    {I_FLDZ, 0, {0,0,0,0}, "\2\xD9\xEE", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMADDPD[] = {
    {I_FMADDPD, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x01\132", IF_SSE5|IF_AMD},
    {I_FMADDPD, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x01\123", IF_SSE5|IF_AMD},
    {I_FMADDPD, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x05\121", IF_SSE5|IF_AMD},
    {I_FMADDPD, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x05\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMADDPS[] = {
    {I_FMADDPS, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\2\x0F\x24\170\132", IF_SSE5|IF_AMD},
    {I_FMADDPS, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\2\x0F\x24\170\123", IF_SSE5|IF_AMD},
    {I_FMADDPS, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x04\121", IF_SSE5|IF_AMD},
    {I_FMADDPS, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x04\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMADDSD[] = {
    {I_FMADDSD, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x03\132", IF_SSE5|IF_AMD},
    {I_FMADDSD, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x03\123", IF_SSE5|IF_AMD},
    {I_FMADDSD, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x07\121", IF_SSE5|IF_AMD},
    {I_FMADDSD, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x07\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMADDSS[] = {
    {I_FMADDSS, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x02\132", IF_SSE5|IF_AMD},
    {I_FMADDSS, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x02\123", IF_SSE5|IF_AMD},
    {I_FMADDSS, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x06\121", IF_SSE5|IF_AMD},
    {I_FMADDSS, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x06\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMNADDPD[] = {
    {I_FMNADDPD, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x11\132", IF_SSE5|IF_AMD},
    {I_FMNADDPD, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x11\123", IF_SSE5|IF_AMD},
    {I_FMNADDPD, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x15\121", IF_SSE5|IF_AMD},
    {I_FMNADDPD, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x15\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMNADDPS[] = {
    {I_FMNADDPS, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x10\132", IF_SSE5|IF_AMD},
    {I_FMNADDPS, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x10\123", IF_SSE5|IF_AMD},
    {I_FMNADDPS, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x14\121", IF_SSE5|IF_AMD},
    {I_FMNADDPS, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x14\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMNADDSD[] = {
    {I_FMNADDSD, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x13\132", IF_SSE5|IF_AMD},
    {I_FMNADDSD, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x13\123", IF_SSE5|IF_AMD},
    {I_FMNADDSD, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x17\121", IF_SSE5|IF_AMD},
    {I_FMNADDSD, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x17\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMNADDSS[] = {
    {I_FMNADDSS, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x12\132", IF_SSE5|IF_AMD},
    {I_FMNADDSS, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x12\123", IF_SSE5|IF_AMD},
    {I_FMNADDSS, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x16\121", IF_SSE5|IF_AMD},
    {I_FMNADDSS, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x16\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMNSUBPD[] = {
    {I_FMNSUBPD, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x19\132", IF_SSE5|IF_AMD},
    {I_FMNSUBPD, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x19\123", IF_SSE5|IF_AMD},
    {I_FMNSUBPD, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x1D\121", IF_SSE5|IF_AMD},
    {I_FMNSUBPD, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x1D\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMNSUBPS[] = {
    {I_FMNSUBPS, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x18\132", IF_SSE5|IF_AMD},
    {I_FMNSUBPS, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x18\123", IF_SSE5|IF_AMD},
    {I_FMNSUBPS, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x1C\121", IF_SSE5|IF_AMD},
    {I_FMNSUBPS, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x1C\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMNSUBSD[] = {
    {I_FMNSUBSD, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x1B\132", IF_SSE5|IF_AMD},
    {I_FMNSUBSD, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x1B\123", IF_SSE5|IF_AMD},
    {I_FMNSUBSD, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x1F\121", IF_SSE5|IF_AMD},
    {I_FMNSUBSD, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x1F\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMNSUBSS[] = {
    {I_FMNSUBSS, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x1A\132", IF_SSE5|IF_AMD},
    {I_FMNSUBSS, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x1A\123", IF_SSE5|IF_AMD},
    {I_FMNSUBSS, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x1E\121", IF_SSE5|IF_AMD},
    {I_FMNSUBSS, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x1E\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMSUBPD[] = {
    {I_FMSUBPD, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x09\132", IF_SSE5|IF_AMD},
    {I_FMSUBPD, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x09\123", IF_SSE5|IF_AMD},
    {I_FMSUBPD, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x0D\121", IF_SSE5|IF_AMD},
    {I_FMSUBPD, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x0D\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMSUBPS[] = {
    {I_FMSUBPS, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x08\132", IF_SSE5|IF_AMD},
    {I_FMSUBPS, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x08\123", IF_SSE5|IF_AMD},
    {I_FMSUBPS, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x0C\121", IF_SSE5|IF_AMD},
    {I_FMSUBPS, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x0C\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMSUBSD[] = {
    {I_FMSUBSD, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x0B\132", IF_SSE5|IF_AMD},
    {I_FMSUBSD, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x0B\123", IF_SSE5|IF_AMD},
    {I_FMSUBSD, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x0F\121", IF_SSE5|IF_AMD},
    {I_FMSUBSD, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x0F\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMSUBSS[] = {
    {I_FMSUBSS, 4, {XMMREG,SAME_AS|0,XMMREG,RM_XMM}, "\160\3\x0F\x24\x0A\132", IF_SSE5|IF_AMD},
    {I_FMSUBSS, 4, {XMMREG,SAME_AS|0,RM_XMM,XMMREG}, "\164\3\x0F\x24\x0A\123", IF_SSE5|IF_AMD},
    {I_FMSUBSS, 4, {XMMREG,XMMREG,RM_XMM,SAME_AS|0}, "\160\3\x0F\x24\x0E\121", IF_SSE5|IF_AMD},
    {I_FMSUBSS, 4, {XMMREG,RM_XMM,XMMREG,SAME_AS|0}, "\164\3\x0F\x24\x0E\112", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMUL[] = {
    {I_FMUL, 1, {MEMORY|BITS32,0,0,0}, "\1\xD8\201", IF_8086|IF_FPU},
    {I_FMUL, 1, {MEMORY|BITS64,0,0,0}, "\1\xDC\201", IF_8086|IF_FPU},
    {I_FMUL, 1, {FPUREG|TO,0,0,0}, "\1\xDC\10\xC8", IF_8086|IF_FPU},
    {I_FMUL, 2, {FPUREG,FPU0,0,0}, "\1\xDC\10\xC8", IF_8086|IF_FPU},
    {I_FMUL, 1, {FPUREG,0,0,0}, "\1\xD8\10\xC8", IF_8086|IF_FPU},
    {I_FMUL, 2, {FPU0,FPUREG,0,0}, "\1\xD8\11\xC8", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FMULP[] = {
    {I_FMULP, 1, {FPUREG,0,0,0}, "\1\xDE\10\xC8", IF_8086|IF_FPU},
    {I_FMULP, 2, {FPUREG,FPU0,0,0}, "\1\xDE\10\xC8", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FNCLEX[] = {
    {I_FNCLEX, 0, {0,0,0,0}, "\2\xDB\xE2", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FNDISI[] = {
    {I_FNDISI, 0, {0,0,0,0}, "\2\xDB\xE1", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FNENI[] = {
    {I_FNENI, 0, {0,0,0,0}, "\2\xDB\xE0", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FNINIT[] = {
    {I_FNINIT, 0, {0,0,0,0}, "\2\xDB\xE3", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FNOP[] = {
    {I_FNOP, 0, {0,0,0,0}, "\2\xD9\xD0", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FNSAVE[] = {
    {I_FNSAVE, 1, {MEMORY,0,0,0}, "\1\xDD\206", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FNSTCW[] = {
    {I_FNSTCW, 1, {MEMORY,0,0,0}, "\1\xD9\207", IF_8086|IF_FPU|IF_SW},
    ITEMPLATE_END
};

static const struct itemplate instrux_FNSTENV[] = {
    {I_FNSTENV, 1, {MEMORY,0,0,0}, "\1\xD9\206", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FNSTSW[] = {
    {I_FNSTSW, 1, {MEMORY,0,0,0}, "\1\xDD\207", IF_8086|IF_FPU|IF_SW},
    {I_FNSTSW, 1, {REG_AX,0,0,0}, "\2\xDF\xE0", IF_286|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FPATAN[] = {
    {I_FPATAN, 0, {0,0,0,0}, "\2\xD9\xF3", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FPREM[] = {
    {I_FPREM, 0, {0,0,0,0}, "\2\xD9\xF8", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FPREM1[] = {
    {I_FPREM1, 0, {0,0,0,0}, "\2\xD9\xF5", IF_386|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FPTAN[] = {
    {I_FPTAN, 0, {0,0,0,0}, "\2\xD9\xF2", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FRCZPD[] = {
    {I_FRCZPD, 2, {XMMREG,RM_XMM,0,0}, "\3\x0F\x7A\x11\110", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FRCZPS[] = {
    {I_FRCZPS, 2, {XMMREG,RM_XMM,0,0}, "\3\x0F\x7A\x10\110", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FRCZSD[] = {
    {I_FRCZSD, 2, {XMMREG,RM_XMM,0,0}, "\3\x0F\x7A\x13\110", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FRCZSS[] = {
    {I_FRCZSS, 2, {XMMREG,RM_XMM,0,0}, "\3\x0F\x7A\x12\110", IF_SSE5|IF_AMD},
    ITEMPLATE_END
};

static const struct itemplate instrux_FRNDINT[] = {
    {I_FRNDINT, 0, {0,0,0,0}, "\2\xD9\xFC", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FRSTOR[] = {
    {I_FRSTOR, 1, {MEMORY,0,0,0}, "\1\xDD\204", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSAVE[] = {
    {I_FSAVE, 1, {MEMORY,0,0,0}, "\2\x9B\xDD\206", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSCALE[] = {
    {I_FSCALE, 0, {0,0,0,0}, "\2\xD9\xFD", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSETPM[] = {
    {I_FSETPM, 0, {0,0,0,0}, "\2\xDB\xE4", IF_286|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSIN[] = {
    {I_FSIN, 0, {0,0,0,0}, "\2\xD9\xFE", IF_386|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSINCOS[] = {
    {I_FSINCOS, 0, {0,0,0,0}, "\2\xD9\xFB", IF_386|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSQRT[] = {
    {I_FSQRT, 0, {0,0,0,0}, "\2\xD9\xFA", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FST[] = {
    {I_FST, 1, {MEMORY|BITS32,0,0,0}, "\1\xD9\202", IF_8086|IF_FPU},
    {I_FST, 1, {MEMORY|BITS64,0,0,0}, "\1\xDD\202", IF_8086|IF_FPU},
    {I_FST, 1, {FPUREG,0,0,0}, "\1\xDD\10\xD0", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSTCW[] = {
    {I_FSTCW, 1, {MEMORY,0,0,0}, "\2\x9B\xD9\207", IF_8086|IF_FPU|IF_SW},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSTENV[] = {
    {I_FSTENV, 1, {MEMORY,0,0,0}, "\2\x9B\xD9\206", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSTP[] = {
    {I_FSTP, 1, {MEMORY|BITS32,0,0,0}, "\1\xD9\203", IF_8086|IF_FPU},
    {I_FSTP, 1, {MEMORY|BITS64,0,0,0}, "\1\xDD\203", IF_8086|IF_FPU},
    {I_FSTP, 1, {MEMORY|BITS80,0,0,0}, "\1\xDB\207", IF_8086|IF_FPU},
    {I_FSTP, 1, {FPUREG,0,0,0}, "\1\xDD\10\xD8", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSTSW[] = {
    {I_FSTSW, 1, {MEMORY,0,0,0}, "\2\x9B\xDD\207", IF_8086|IF_FPU|IF_SW},
    {I_FSTSW, 1, {REG_AX,0,0,0}, "\3\x9B\xDF\xE0", IF_286|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSUB[] = {
    {I_FSUB, 1, {MEMORY|BITS32,0,0,0}, "\1\xD8\204", IF_8086|IF_FPU},
    {I_FSUB, 1, {MEMORY|BITS64,0,0,0}, "\1\xDC\204", IF_8086|IF_FPU},
    {I_FSUB, 1, {FPUREG|TO,0,0,0}, "\1\xDC\10\xE8", IF_8086|IF_FPU},
    {I_FSUB, 2, {FPUREG,FPU0,0,0}, "\1\xDC\10\xE8", IF_8086|IF_FPU},
    {I_FSUB, 1, {FPUREG,0,0,0}, "\1\xD8\10\xE0", IF_8086|IF_FPU},
    {I_FSUB, 2, {FPU0,FPUREG,0,0}, "\1\xD8\11\xE0", IF_8086|IF_FPU},
    ITEMPLATE_END
};

static const struct itemplate instrux_FSUBP[] = {
    {I_FSUBP, 1, {FPUREG,0,0,0}, "\1\xDE\10\xE8", IF_8086|IF_FPU},
    {I_FSUBP, 2, {FPUREG,FPU0,0,0
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -