📄 insnsa.c
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{I_CMPXCHG486, 2, {MEMORY,REG16,0,0}, "\320\2\x0F\xA7\101", IF_486|IF_SM|IF_UNDOC},
{I_CMPXCHG486, 2, {REG16,REG16,0,0}, "\320\2\x0F\xA7\101", IF_486|IF_UNDOC},
{I_CMPXCHG486, 2, {MEMORY,REG32,0,0}, "\321\2\x0F\xA7\101", IF_486|IF_SM|IF_UNDOC},
{I_CMPXCHG486, 2, {REG32,REG32,0,0}, "\321\2\x0F\xA7\101", IF_486|IF_UNDOC},
ITEMPLATE_END
};
static const struct itemplate instrux_CMPXCHG8B[] = {
{I_CMPXCHG8B, 1, {MEMORY,0,0,0}, "\2\x0F\xC7\201", IF_PENT},
ITEMPLATE_END
};
static const struct itemplate instrux_COMISD[] = {
{I_COMISD, 2, {XMMREG,RM_XMM,0,0}, "\331\366\2\x0F\x2F\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_COMISS[] = {
{I_COMISS, 2, {XMMREG,RM_XMM,0,0}, "\2\x0F\x2F\110", IF_KATMAI|IF_SSE},
ITEMPLATE_END
};
static const struct itemplate instrux_COMPD[] = {
{I_COMPD, 4, {XMMREG,XMMREG,RM_XMM,IMMEDIATE}, "\160\3\x0F\x25\x2D\121\27", IF_SSE5|IF_AMD},
ITEMPLATE_END
};
static const struct itemplate instrux_COMPS[] = {
{I_COMPS, 4, {XMMREG,XMMREG,RM_XMM,IMMEDIATE}, "\160\3\x0F\x25\x2C\121\27", IF_SSE5|IF_AMD},
ITEMPLATE_END
};
static const struct itemplate instrux_COMSD[] = {
{I_COMSD, 4, {XMMREG,XMMREG,RM_XMM,IMMEDIATE}, "\160\3\x0F\x25\x2F\121\27", IF_SSE5|IF_AMD},
ITEMPLATE_END
};
static const struct itemplate instrux_COMSS[] = {
{I_COMSS, 4, {XMMREG,XMMREG,RM_XMM,IMMEDIATE}, "\160\3\x0F\x25\x2E\121\27", IF_SSE5|IF_AMD},
ITEMPLATE_END
};
static const struct itemplate instrux_CPUID[] = {
{I_CPUID, 0, {0,0,0,0}, "\2\x0F\xA2", IF_PENT},
ITEMPLATE_END
};
static const struct itemplate instrux_CPU_READ[] = {
{I_CPU_READ, 0, {0,0,0,0}, "\2\x0F\x3D", IF_PENT|IF_CYRIX},
ITEMPLATE_END
};
static const struct itemplate instrux_CPU_WRITE[] = {
{I_CPU_WRITE, 0, {0,0,0,0}, "\2\x0F\x3C", IF_PENT|IF_CYRIX},
ITEMPLATE_END
};
static const struct itemplate instrux_CQO[] = {
{I_CQO, 0, {0,0,0,0}, "\324\1\x99", IF_X64},
ITEMPLATE_END
};
static const struct itemplate instrux_CRC32[] = {
{I_CRC32, 2, {REG32,RM_GPR|BITS8,0,0}, "\332\3\x0F\x38\1\xF0\110", IF_SSE42},
{I_CRC32, 2, {REG32,RM_GPR|BITS16,0,0}, "\332\3\x0F\x38\1\xF1\110", IF_SSE42},
{I_CRC32, 2, {REG32,RM_GPR|BITS32,0,0}, "\332\3\x0F\x38\1\xF1\110", IF_SSE42},
{I_CRC32, 2, {REG64,RM_GPR|BITS8,0,0}, "\324\332\3\x0F\x38\1\xF0\110", IF_SSE42|IF_X64},
{I_CRC32, 2, {REG64,RM_GPR|BITS64,0,0}, "\324\332\3\x0F\x38\1\xF1\110", IF_SSE42|IF_X64},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTDQ2PD[] = {
{I_CVTDQ2PD, 2, {XMMREG,RM_XMM,0,0}, "\333\2\x0F\xE6\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTDQ2PS[] = {
{I_CVTDQ2PS, 2, {XMMREG,RM_XMM,0,0}, "\2\x0F\x5B\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPD2DQ[] = {
{I_CVTPD2DQ, 2, {XMMREG,RM_XMM,0,0}, "\332\2\x0F\xE6\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPD2PI[] = {
{I_CVTPD2PI, 2, {MMXREG,RM_XMM,0,0}, "\366\2\x0F\x2D\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPD2PS[] = {
{I_CVTPD2PS, 2, {XMMREG,RM_XMM,0,0}, "\366\2\x0F\x5A\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPH2PS[] = {
{I_CVTPH2PS, 2, {XMMREG,RM_XMM,0,0}, "\3\x0F\x7A\x30\110", IF_SSE5|IF_AMD|IF_SQ},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPI2PD[] = {
{I_CVTPI2PD, 2, {XMMREG,RM_MMX,0,0}, "\366\2\x0F\x2A\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPI2PS[] = {
{I_CVTPI2PS, 2, {XMMREG,RM_MMX,0,0}, "\331\2\x0F\x2A\110", IF_KATMAI|IF_SSE|IF_MMX},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPS2DQ[] = {
{I_CVTPS2DQ, 2, {XMMREG,RM_XMM,0,0}, "\366\2\x0F\x5B\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPS2PD[] = {
{I_CVTPS2PD, 2, {XMMREG,RM_XMM,0,0}, "\2\x0F\x5A\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPS2PH[] = {
{I_CVTPS2PH, 2, {RM_XMM,XMMREG,0,0}, "\3\x0F\x7A\x31\101", IF_SSE5|IF_AMD|IF_SQ},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTPS2PI[] = {
{I_CVTPS2PI, 2, {MMXREG,RM_XMM,0,0}, "\331\2\x0F\x2D\110", IF_KATMAI|IF_SSE|IF_MMX},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTSD2SI[] = {
{I_CVTSD2SI, 2, {REG32,RM_XMM,0,0}, "\332\2\x0F\x2D\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTSD2SS[] = {
{I_CVTSD2SS, 2, {XMMREG,RM_XMM,0,0}, "\332\2\x0F\x5A\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTSI2SD[] = {
{I_CVTSI2SD, 2, {XMMREG,REG32,0,0}, "\332\2\x0F\x2A\110", IF_WILLAMETTE|IF_SSE2},
{I_CVTSI2SD, 2, {XMMREG,MEMORY,0,0}, "\332\2\x0F\x2A\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTSI2SS[] = {
{I_CVTSI2SS, 2, {XMMREG,MEMORY,0,0}, "\333\2\x0F\x2A\110", IF_KATMAI|IF_SSE|IF_SD|IF_AR1},
{I_CVTSI2SS, 2, {XMMREG,REG32,0,0}, "\333\2\x0F\x2A\110", IF_KATMAI|IF_SSE},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTSS2SD[] = {
{I_CVTSS2SD, 2, {XMMREG,RM_XMM,0,0}, "\333\2\x0F\x5A\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTSS2SI[] = {
{I_CVTSS2SI, 2, {REG32,RM_XMM,0,0}, "\333\2\x0F\x2D\110", IF_KATMAI|IF_SSE},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTTPD2DQ[] = {
{I_CVTTPD2DQ, 2, {XMMREG,RM_XMM,0,0}, "\366\2\x0F\xE6\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTTPD2PI[] = {
{I_CVTTPD2PI, 2, {MMXREG,RM_XMM,0,0}, "\366\2\x0F\x2C\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTTPS2DQ[] = {
{I_CVTTPS2DQ, 2, {XMMREG,RM_XMM,0,0}, "\333\2\x0F\x5B\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTTPS2PI[] = {
{I_CVTTPS2PI, 2, {MMXREG,RM_XMM,0,0}, "\331\2\x0F\x2C\110", IF_KATMAI|IF_SSE|IF_MMX},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTTSD2SI[] = {
{I_CVTTSD2SI, 2, {REG32,RM_XMM,0,0}, "\332\2\x0F\x2C\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_CVTTSS2SI[] = {
{I_CVTTSS2SI, 2, {REG32,RM_XMM,0,0}, "\333\2\x0F\x2C\110", IF_KATMAI|IF_SSE},
ITEMPLATE_END
};
static const struct itemplate instrux_CWD[] = {
{I_CWD, 0, {0,0,0,0}, "\320\1\x99", IF_8086},
ITEMPLATE_END
};
static const struct itemplate instrux_CWDE[] = {
{I_CWDE, 0, {0,0,0,0}, "\321\1\x98", IF_386},
ITEMPLATE_END
};
static const struct itemplate instrux_DAA[] = {
{I_DAA, 0, {0,0,0,0}, "\1\x27", IF_8086|IF_NOLONG},
ITEMPLATE_END
};
static const struct itemplate instrux_DAS[] = {
{I_DAS, 0, {0,0,0,0}, "\1\x2F", IF_8086|IF_NOLONG},
ITEMPLATE_END
};
static const struct itemplate instrux_DB[] = {
ITEMPLATE_END
};
static const struct itemplate instrux_DD[] = {
ITEMPLATE_END
};
static const struct itemplate instrux_DEC[] = {
{I_DEC, 1, {REG16,0,0,0}, "\320\10\x48", IF_8086|IF_NOLONG},
{I_DEC, 1, {REG32,0,0,0}, "\321\10\x48", IF_386|IF_NOLONG},
{I_DEC, 1, {RM_GPR|BITS8,0,0,0}, "\1\xFE\201", IF_8086},
{I_DEC, 1, {RM_GPR|BITS16,0,0,0}, "\320\1\xFF\201", IF_8086},
{I_DEC, 1, {RM_GPR|BITS32,0,0,0}, "\321\1\xFF\201", IF_386},
{I_DEC, 1, {RM_GPR|BITS64,0,0,0}, "\324\1\xFF\201", IF_X64},
ITEMPLATE_END
};
static const struct itemplate instrux_DIV[] = {
{I_DIV, 1, {RM_GPR|BITS8,0,0,0}, "\1\xF6\206", IF_8086},
{I_DIV, 1, {RM_GPR|BITS16,0,0,0}, "\320\1\xF7\206", IF_8086},
{I_DIV, 1, {RM_GPR|BITS32,0,0,0}, "\321\1\xF7\206", IF_386},
{I_DIV, 1, {RM_GPR|BITS64,0,0,0}, "\324\1\xF7\206", IF_X64},
ITEMPLATE_END
};
static const struct itemplate instrux_DIVPD[] = {
{I_DIVPD, 2, {XMMREG,RM_XMM,0,0}, "\366\2\x0F\x5E\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
ITEMPLATE_END
};
static const struct itemplate instrux_DIVPS[] = {
{I_DIVPS, 2, {XMMREG,RM_XMM,0,0}, "\331\2\x0F\x5E\110", IF_KATMAI|IF_SSE},
ITEMPLATE_END
};
static const struct itemplate instrux_DIVSD[] = {
{I_DIVSD, 2, {XMMREG,RM_XMM,0,0}, "\332\2\x0F\x5E\110", IF_WILLAMETTE|IF_SSE2},
ITEMPLATE_END
};
static const struct itemplate instrux_DIVSS[] = {
{I_DIVSS, 2, {XMMREG,RM_XMM,0,0}, "\333\2\x0F\x5E\110", IF_KATMAI|IF_SSE},
ITEMPLATE_END
};
static const struct itemplate instrux_DMINT[] = {
{I_DMINT, 0, {0,0,0,0}, "\2\x0F\x39", IF_P6|IF_CYRIX},
ITEMPLATE_END
};
static const struct itemplate instrux_DO[] = {
ITEMPLATE_END
};
static const struct itemplate instrux_DPPD[] = {
{I_DPPD, 3, {XMMREG,RM_XMM,IMMEDIATE,0}, "\366\3\x0F\x3A\x41\110\26", IF_SSE41},
ITEMPLATE_END
};
static const struct itemplate instrux_DPPS[] = {
{I_DPPS, 3, {XMMREG,RM_XMM,IMMEDIATE,0}, "\366\3\x0F\x3A\x40\110\26", IF_SSE41},
ITEMPLATE_END
};
static const struct itemplate instrux_DQ[] = {
ITEMPLATE_END
};
static const struct itemplate instrux_DT[] = {
ITEMPLATE_END
};
static const struct itemplate instrux_DW[] = {
ITEMPLATE_END
};
static const struct itemplate instrux_EMMS[] = {
{I_EMMS, 0, {0,0,0,0}, "\2\x0F\x77", IF_PENT|IF_MMX},
ITEMPLATE_END
};
static const struct itemplate instrux_ENTER[] = {
{I_ENTER, 2, {IMMEDIATE,IMMEDIATE,0,0}, "\1\xC8\30\25", IF_186},
ITEMPLATE_END
};
static const struct itemplate instrux_EQU[] = {
{I_EQU, 1, {IMMEDIATE,0,0,0}, "\0", IF_8086},
{I_EQU, 2, {IMMEDIATE|COLON,IMMEDIATE,0,0}, "\0", IF_8086},
ITEMPLATE_END
};
static const struct itemplate instrux_EXTRACTPS[] = {
{I_EXTRACTPS, 3, {RM_GPR|BITS32,XMMREG,IMMEDIATE,0}, "\366\3\x0F\x3A\x17\101\26", IF_SSE41},
{I_EXTRACTPS, 3, {REG64,XMMREG,IMMEDIATE,0}, "\324\366\3\x0F\x3A\x17\101\26", IF_SSE41|IF_X64},
ITEMPLATE_END
};
static const struct itemplate instrux_EXTRQ[] = {
{I_EXTRQ, 3, {XMMREG,IMMEDIATE,IMMEDIATE,0}, "\366\2\x0F\x78\200\25\26", IF_SSE4A|IF_AMD},
{I_EXTRQ, 2, {XMMREG,XMMREG,0,0}, "\366\2\x0F\x79\110", IF_SSE4A|IF_AMD},
ITEMPLATE_END
};
static const struct itemplate instrux_F2XM1[] = {
{I_F2XM1, 0, {0,0,0,0}, "\2\xD9\xF0", IF_8086|IF_FPU},
ITEMPLATE_END
};
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