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📄 insnsa.c

📁 nasm早期的源代码,比较简单是学习汇编和编译原理的好例子
💻 C
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/* This file auto-generated from insns.dat by insns.pl - don't edit it */

#include "nasm.h"
#include "insns.h"

static const struct itemplate instrux_AAA[] = {
    {I_AAA, 0, {0,0,0,0}, "\1\x37", IF_8086|IF_NOLONG},
    ITEMPLATE_END
};

static const struct itemplate instrux_AAD[] = {
    {I_AAD, 0, {0,0,0,0}, "\2\xD5\x0A", IF_8086|IF_NOLONG},
    {I_AAD, 1, {IMMEDIATE,0,0,0}, "\1\xD5\24", IF_8086|IF_SB|IF_NOLONG},
    ITEMPLATE_END
};

static const struct itemplate instrux_AAM[] = {
    {I_AAM, 0, {0,0,0,0}, "\2\xD4\x0A", IF_8086|IF_NOLONG},
    {I_AAM, 1, {IMMEDIATE,0,0,0}, "\1\xD4\24", IF_8086|IF_SB|IF_NOLONG},
    ITEMPLATE_END
};

static const struct itemplate instrux_AAS[] = {
    {I_AAS, 0, {0,0,0,0}, "\1\x3F", IF_8086|IF_NOLONG},
    ITEMPLATE_END
};

static const struct itemplate instrux_ADC[] = {
    {I_ADC, 2, {MEMORY,REG8,0,0}, "\1\x10\101", IF_8086|IF_SM},
    {I_ADC, 2, {REG8,REG8,0,0}, "\1\x10\101", IF_8086},
    {I_ADC, 2, {MEMORY,REG16,0,0}, "\320\1\x11\101", IF_8086|IF_SM},
    {I_ADC, 2, {REG16,REG16,0,0}, "\320\1\x11\101", IF_8086},
    {I_ADC, 2, {MEMORY,REG32,0,0}, "\321\1\x11\101", IF_386|IF_SM},
    {I_ADC, 2, {REG32,REG32,0,0}, "\321\1\x11\101", IF_386},
    {I_ADC, 2, {MEMORY,REG64,0,0}, "\324\1\x11\101", IF_X64|IF_SM},
    {I_ADC, 2, {REG64,REG64,0,0}, "\324\1\x11\101", IF_X64},
    {I_ADC, 2, {REG8,MEMORY,0,0}, "\1\x12\110", IF_8086|IF_SM},
    {I_ADC, 2, {REG8,REG8,0,0}, "\1\x12\110", IF_8086},
    {I_ADC, 2, {REG16,MEMORY,0,0}, "\320\1\x13\110", IF_8086|IF_SM},
    {I_ADC, 2, {REG16,REG16,0,0}, "\320\1\x13\110", IF_8086},
    {I_ADC, 2, {REG32,MEMORY,0,0}, "\321\1\x13\110", IF_386|IF_SM},
    {I_ADC, 2, {REG32,REG32,0,0}, "\321\1\x13\110", IF_386},
    {I_ADC, 2, {REG64,MEMORY,0,0}, "\324\1\x13\110", IF_X64|IF_SM},
    {I_ADC, 2, {REG64,REG64,0,0}, "\324\1\x13\110", IF_X64},
    {I_ADC, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0}, "\320\1\x83\202\15", IF_8086},
    {I_ADC, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, "\321\1\x83\202\15", IF_386},
    {I_ADC, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, "\324\1\x83\202\15", IF_X64},
    {I_ADC, 2, {REG_AL,IMMEDIATE,0,0}, "\1\x14\21", IF_8086|IF_SM},
    {I_ADC, 2, {REG_AX,SBYTE,0,0}, "\320\1\x83\202\15", IF_8086|IF_SM},
    {I_ADC, 2, {REG_AX,IMMEDIATE,0,0}, "\320\1\x15\31", IF_8086|IF_SM},
    {I_ADC, 2, {REG_EAX,SBYTE,0,0}, "\321\1\x83\202\15", IF_386|IF_SM},
    {I_ADC, 2, {REG_EAX,IMMEDIATE,0,0}, "\321\1\x15\41", IF_386|IF_SM},
    {I_ADC, 2, {REG_RAX,SBYTE,0,0}, "\321\1\x83\202\15", IF_X64|IF_SM},
    {I_ADC, 2, {REG_RAX,IMMEDIATE,0,0}, "\321\1\x15\41", IF_X64|IF_SM},
    {I_ADC, 2, {RM_GPR|BITS8,IMMEDIATE,0,0}, "\1\x80\202\21", IF_8086|IF_SM},
    {I_ADC, 2, {RM_GPR|BITS16,IMMEDIATE,0,0}, "\320\145\1\x81\202\141", IF_8086|IF_SM},
    {I_ADC, 2, {RM_GPR|BITS32,IMMEDIATE,0,0}, "\321\155\1\x81\202\151", IF_386|IF_SM},
    {I_ADC, 2, {RM_GPR|BITS64,IMMEDIATE,0,0}, "\324\155\1\x81\202\151", IF_X64|IF_SM},
    {I_ADC, 2, {MEMORY,IMMEDIATE|BITS8,0,0}, "\1\x80\202\21", IF_8086|IF_SM},
    {I_ADC, 2, {MEMORY,IMMEDIATE|BITS16,0,0}, "\320\145\1\x81\202\141", IF_8086|IF_SM},
    {I_ADC, 2, {MEMORY,IMMEDIATE|BITS32,0,0}, "\321\155\1\x81\202\151", IF_386|IF_SM},
    ITEMPLATE_END
};

static const struct itemplate instrux_ADD[] = {
    {I_ADD, 2, {MEMORY,REG8,0,0}, "\170\101", IF_8086|IF_SM},
    {I_ADD, 2, {REG8,REG8,0,0}, "\170\101", IF_8086},
    {I_ADD, 2, {MEMORY,REG16,0,0}, "\320\1\x01\101", IF_8086|IF_SM},
    {I_ADD, 2, {REG16,REG16,0,0}, "\320\1\x01\101", IF_8086},
    {I_ADD, 2, {MEMORY,REG32,0,0}, "\321\1\x01\101", IF_386|IF_SM},
    {I_ADD, 2, {REG32,REG32,0,0}, "\321\1\x01\101", IF_386},
    {I_ADD, 2, {MEMORY,REG64,0,0}, "\324\1\x01\101", IF_X64|IF_SM},
    {I_ADD, 2, {REG64,REG64,0,0}, "\324\1\x01\101", IF_X64},
    {I_ADD, 2, {REG8,MEMORY,0,0}, "\1\x02\110", IF_8086|IF_SM},
    {I_ADD, 2, {REG8,REG8,0,0}, "\1\x02\110", IF_8086},
    {I_ADD, 2, {REG16,MEMORY,0,0}, "\320\1\x03\110", IF_8086|IF_SM},
    {I_ADD, 2, {REG16,REG16,0,0}, "\320\1\x03\110", IF_8086},
    {I_ADD, 2, {REG32,MEMORY,0,0}, "\321\1\x03\110", IF_386|IF_SM},
    {I_ADD, 2, {REG32,REG32,0,0}, "\321\1\x03\110", IF_386},
    {I_ADD, 2, {REG64,MEMORY,0,0}, "\324\1\x03\110", IF_X64|IF_SM},
    {I_ADD, 2, {REG64,REG64,0,0}, "\324\1\x03\110", IF_X64},
    {I_ADD, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0}, "\320\1\x83\200\15", IF_8086},
    {I_ADD, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, "\321\1\x83\200\15", IF_386},
    {I_ADD, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, "\324\1\x83\200\15", IF_X64},
    {I_ADD, 2, {REG_AL,IMMEDIATE,0,0}, "\1\x04\21", IF_8086|IF_SM},
    {I_ADD, 2, {REG_AX,SBYTE,0,0}, "\320\1\x83\200\15", IF_8086|IF_SM},
    {I_ADD, 2, {REG_AX,IMMEDIATE,0,0}, "\320\1\x05\31", IF_8086|IF_SM},
    {I_ADD, 2, {REG_EAX,SBYTE,0,0}, "\321\1\x83\200\15", IF_386|IF_SM},
    {I_ADD, 2, {REG_EAX,IMMEDIATE,0,0}, "\321\1\x05\41", IF_386|IF_SM},
    {I_ADD, 2, {REG_RAX,SBYTE,0,0}, "\321\1\x83\200\15", IF_X64|IF_SM},
    {I_ADD, 2, {REG_RAX,IMMEDIATE,0,0}, "\323\1\x05\41", IF_X64|IF_SM},
    {I_ADD, 2, {RM_GPR|BITS8,IMMEDIATE,0,0}, "\1\x80\200\21", IF_8086|IF_SM},
    {I_ADD, 2, {RM_GPR|BITS16,IMMEDIATE,0,0}, "\320\145\1\x81\200\141", IF_8086|IF_SM},
    {I_ADD, 2, {RM_GPR|BITS32,IMMEDIATE,0,0}, "\321\155\1\x81\200\151", IF_386|IF_SM},
    {I_ADD, 2, {RM_GPR|BITS64,IMMEDIATE,0,0}, "\324\155\1\x81\200\151", IF_X64|IF_SM},
    {I_ADD, 2, {MEMORY,IMMEDIATE|BITS8,0,0}, "\1\x80\200\21", IF_8086|IF_SM},
    {I_ADD, 2, {MEMORY,IMMEDIATE|BITS16,0,0}, "\320\145\1\x81\200\141", IF_8086|IF_SM},
    {I_ADD, 2, {MEMORY,IMMEDIATE|BITS32,0,0}, "\321\155\1\x81\200\151", IF_386|IF_SM},
    ITEMPLATE_END
};

static const struct itemplate instrux_ADDPD[] = {
    {I_ADDPD, 2, {XMMREG,RM_XMM,0,0}, "\331\366\2\x0F\x58\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
    ITEMPLATE_END
};

static const struct itemplate instrux_ADDPS[] = {
    {I_ADDPS, 2, {XMMREG,RM_XMM,0,0}, "\331\2\x0F\x58\110", IF_KATMAI|IF_SSE},
    ITEMPLATE_END
};

static const struct itemplate instrux_ADDSD[] = {
    {I_ADDSD, 2, {XMMREG,RM_XMM,0,0}, "\331\332\2\x0F\x58\110", IF_WILLAMETTE|IF_SSE2},
    ITEMPLATE_END
};

static const struct itemplate instrux_ADDSS[] = {
    {I_ADDSS, 2, {XMMREG,RM_XMM,0,0}, "\333\2\x0F\x58\110", IF_KATMAI|IF_SSE},
    ITEMPLATE_END
};

static const struct itemplate instrux_ADDSUBPD[] = {
    {I_ADDSUBPD, 2, {XMMREG,RM_XMM,0,0}, "\366\2\x0F\xD0\110", IF_PRESCOTT|IF_SSE3|IF_SM},
    ITEMPLATE_END
};

static const struct itemplate instrux_ADDSUBPS[] = {
    {I_ADDSUBPS, 2, {XMMREG,RM_XMM,0,0}, "\332\2\x0F\xD0\110", IF_PRESCOTT|IF_SSE3|IF_SM},
    ITEMPLATE_END
};

static const struct itemplate instrux_AND[] = {
    {I_AND, 2, {MEMORY,REG8,0,0}, "\1\x20\101", IF_8086|IF_SM},
    {I_AND, 2, {REG8,REG8,0,0}, "\1\x20\101", IF_8086},
    {I_AND, 2, {MEMORY,REG16,0,0}, "\320\1\x21\101", IF_8086|IF_SM},
    {I_AND, 2, {REG16,REG16,0,0}, "\320\1\x21\101", IF_8086},
    {I_AND, 2, {MEMORY,REG32,0,0}, "\321\1\x21\101", IF_386|IF_SM},
    {I_AND, 2, {REG32,REG32,0,0}, "\321\1\x21\101", IF_386},
    {I_AND, 2, {MEMORY,REG64,0,0}, "\324\1\x21\101", IF_X64|IF_SM},
    {I_AND, 2, {REG64,REG64,0,0}, "\324\1\x21\101", IF_X64},
    {I_AND, 2, {REG8,MEMORY,0,0}, "\1\x22\110", IF_8086|IF_SM},
    {I_AND, 2, {REG8,REG8,0,0}, "\1\x22\110", IF_8086},
    {I_AND, 2, {REG16,MEMORY,0,0}, "\320\1\x23\110", IF_8086|IF_SM},
    {I_AND, 2, {REG16,REG16,0,0}, "\320\1\x23\110", IF_8086},
    {I_AND, 2, {REG32,MEMORY,0,0}, "\321\1\x23\110", IF_386|IF_SM},
    {I_AND, 2, {REG32,REG32,0,0}, "\321\1\x23\110", IF_386},
    {I_AND, 2, {REG64,MEMORY,0,0}, "\324\1\x23\110", IF_X64|IF_SM},
    {I_AND, 2, {REG64,REG64,0,0}, "\324\1\x23\110", IF_X64},
    {I_AND, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0}, "\320\1\x83\204\15", IF_8086},
    {I_AND, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, "\321\1\x83\204\15", IF_386},
    {I_AND, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, "\324\1\x83\204\15", IF_X64},
    {I_AND, 2, {REG_AL,IMMEDIATE,0,0}, "\1\x24\21", IF_8086|IF_SM},
    {I_AND, 2, {REG_AX,SBYTE,0,0}, "\320\1\x83\204\15", IF_8086|IF_SM},
    {I_AND, 2, {REG_AX,IMMEDIATE,0,0}, "\320\1\x25\31", IF_8086|IF_SM},
    {I_AND, 2, {REG_EAX,SBYTE,0,0}, "\321\1\x83\204\15", IF_386|IF_SM},
    {I_AND, 2, {REG_EAX,IMMEDIATE,0,0}, "\321\1\x25\41", IF_386|IF_SM},
    {I_AND, 2, {REG_RAX,SBYTE,0,0}, "\321\1\x83\204\15", IF_X64|IF_SM},
    {I_AND, 2, {REG_RAX,IMMEDIATE,0,0}, "\324\1\x25\41", IF_X64|IF_SM},
    {I_AND, 2, {RM_GPR|BITS8,IMMEDIATE,0,0}, "\1\x80\204\21", IF_8086|IF_SM},
    {I_AND, 2, {RM_GPR|BITS16,IMMEDIATE,0,0}, "\320\145\1\x81\204\141", IF_8086|IF_SM},
    {I_AND, 2, {RM_GPR|BITS32,IMMEDIATE,0,0}, "\321\155\1\x81\204\151", IF_386|IF_SM},
    {I_AND, 2, {RM_GPR|BITS64,IMMEDIATE,0,0}, "\324\155\1\x81\204\151", IF_X64|IF_SM},
    {I_AND, 2, {MEMORY,IMMEDIATE|BITS8,0,0}, "\1\x80\204\21", IF_8086|IF_SM},
    {I_AND, 2, {MEMORY,IMMEDIATE|BITS16,0,0}, "\320\145\1\x81\204\141", IF_8086|IF_SM},
    {I_AND, 2, {MEMORY,IMMEDIATE|BITS32,0,0}, "\321\155\1\x81\204\151", IF_386|IF_SM},
    ITEMPLATE_END
};

static const struct itemplate instrux_ANDNPD[] = {
    {I_ANDNPD, 2, {XMMREG,RM_XMM,0,0}, "\331\366\2\x0F\x55\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
    ITEMPLATE_END
};

static const struct itemplate instrux_ANDNPS[] = {
    {I_ANDNPS, 2, {XMMREG,RM_XMM,0,0}, "\2\x0F\x55\110", IF_KATMAI|IF_SSE},
    ITEMPLATE_END
};

static const struct itemplate instrux_ANDPD[] = {
    {I_ANDPD, 2, {XMMREG,RM_XMM,0,0}, "\331\366\2\x0F\x54\110", IF_WILLAMETTE|IF_SSE2|IF_SM},
    ITEMPLATE_END
};

static const struct itemplate instrux_ANDPS[] = {
    {I_ANDPS, 2, {XMMREG,RM_XMM,0,0}, "\2\x0F\x54\110", IF_KATMAI|IF_SSE},
    ITEMPLATE_END
};

static const struct itemplate instrux_ARPL[] = {
    {I_ARPL, 2, {MEMORY,REG16,0,0}, "\1\x63\101", IF_286|IF_PROT|IF_SM|IF_NOLONG},
    {I_ARPL, 2, {REG16,REG16,0,0}, "\1\x63\101", IF_286|IF_PROT|IF_NOLONG},
    ITEMPLATE_END
};

static const struct itemplate instrux_BB0_RESET[] = {
    {I_BB0_RESET, 0, {0,0,0,0}, "\2\x0F\x3A", IF_PENT|IF_CYRIX},
    ITEMPLATE_END
};

static const struct itemplate instrux_BB1_RESET[] = {
    {I_BB1_RESET, 0, {0,0,0,0}, "\2\x0F\x3B", IF_PENT|IF_CYRIX},
    ITEMPLATE_END
};

static const struct itemplate instrux_BLENDPD[] = {
    {I_BLENDPD, 3, {XMMREG,RM_XMM,IMMEDIATE,0}, "\366\3\x0F\x3A\x0D\110\26", IF_SSE41},
    ITEMPLATE_END
};

static const struct itemplate instrux_BLENDPS[] = {
    {I_BLENDPS, 3, {XMMREG,RM_XMM,IMMEDIATE,0}, "\366\3\x0F\x3A\x0C\110\26", IF_SSE41},
    ITEMPLATE_END
};

static const struct itemplate instrux_BLENDVPD[] = {
    {I_BLENDVPD, 3, {XMMREG,RM_XMM,XMM0,0}, "\366\3\x0F\x38\x15\110", IF_SSE41},
    ITEMPLATE_END
};

static const struct itemplate instrux_BLENDVPS[] = {
    {I_BLENDVPS, 3, {XMMREG,RM_XMM,XMM0,0}, "\366\3\x0F\x38\x14\110", IF_SSE41},
    ITEMPLATE_END
};

static const struct itemplate instrux_BOUND[] = {
    {I_BOUND, 2, {REG16,MEMORY,0,0}, "\320\1\x62\110", IF_186|IF_NOLONG},
    {I_BOUND, 2, {REG32,MEMORY,0,0}, "\321\1\x62\110", IF_386|IF_NOLONG},
    ITEMPLATE_END
};

static const struct itemplate instrux_BSF[] = {
    {I_BSF, 2, {REG16,MEMORY,0,0}, "\320\2\x0F\xBC\110", IF_386|IF_SM},
    {I_BSF, 2, {REG16,REG16,0,0}, "\320\2\x0F\xBC\110", IF_386},
    {I_BSF, 2, {REG32,MEMORY,0,0}, "\321\2\x0F\xBC\110", IF_386|IF_SM},
    {I_BSF, 2, {REG32,REG32,0,0}, "\321\2\x0F\xBC\110", IF_386},
    {I_BSF, 2, {REG64,MEMORY,0,0}, "\324\2\x0F\xBC\110", IF_X64|IF_SM},
    {I_BSF, 2, {REG64,REG64,0,0}, "\324\2\x0F\xBC\110", IF_X64},
    ITEMPLATE_END
};

static const struct itemplate instrux_BSR[] = {
    {I_BSR, 2, {REG16,MEMORY,0,0}, "\320\2\x0F\xBD\110", IF_386|IF_SM},
    {I_BSR, 2, {REG16,REG16,0,0}, "\320\2\x0F\xBD\110", IF_386},
    {I_BSR, 2, {REG32,MEMORY,0,0}, "\321\2\x0F\xBD\110", IF_386|IF_SM},
    {I_BSR, 2, {REG32,REG32,0,0}, "\321\2\x0F\xBD\110", IF_386},
    {I_BSR, 2, {REG64,MEMORY,0,0}, "\324\2\x0F\xBD\110", IF_X64|IF_SM},
    {I_BSR, 2, {REG64,REG64,0,0}, "\324\2\x0F\xBD\110", IF_X64},
    ITEMPLATE_END
};

static const struct itemplate instrux_BSWAP[] = {
    {I_BSWAP, 1, {REG32,0,0,0}, "\321\1\x0F\10\xC8", IF_486},
    {I_BSWAP, 1, {REG64,0,0,0}, "\324\1\x0F\10\xC8", IF_X64},
    ITEMPLATE_END
};

static const struct itemplate instrux_BT[] = {
    {I_BT, 2, {MEMORY,REG16,0,0}, "\320\2\x0F\xA3\101", IF_386|IF_SM},
    {I_BT, 2, {REG16,REG16,0,0}, "\320\2\x0F\xA3\101", IF_386},
    {I_BT, 2, {MEMORY,REG32,0,0}, "\321\2\x0F\xA3\101", IF_386|IF_SM},
    {I_BT, 2, {REG32,REG32,0,0}, "\321\2\x0F\xA3\101", IF_386},
    {I_BT, 2, {MEMORY,REG64,0,0}, "\324\2\x0F\xA3\101", IF_X64|IF_SM},
    {I_BT, 2, {REG64,REG64,0,0}, "\324\2\x0F\xA3\101", IF_X64},
    {I_BT, 2, {RM_GPR|BITS16,IMMEDIATE,0,0}, "\320\2\x0F\xBA\204\25", IF_386|IF_SB},
    {I_BT, 2, {RM_GPR|BITS32,IMMEDIATE,0,0}, "\321\2\x0F\xBA\204\25", IF_386|IF_SB},
    {I_BT, 2, {RM_GPR|BITS64,IMMEDIATE,0,0}, "\324\2\x0F\xBA\204\25", IF_X64|IF_SB},
    ITEMPLATE_END
};

static const struct itemplate instrux_BTC[] = {
    {I_BTC, 2, {MEMORY,REG16,0,0}, "\320\2\x0F\xBB\101", IF_386|IF_SM},
    {I_BTC, 2, {REG16,REG16,0,0}, "\320\2\x0F\xBB\101", IF_386},
    {I_BTC, 2, {MEMORY,REG32,0,0}, "\321\2\x0F\xBB\101", IF_386|IF_SM},
    {I_BTC, 2, {REG32,REG32,0,0}, "\321\2\x0F\xBB\101", IF_386},
    {I_BTC, 2, {MEMORY,REG64,0,0}, "\324\2\x0F\xBB\101", IF_X64|IF_SM},
    {I_BTC, 2, {REG64,REG64,0,0}, "\324\2\x0F\xBB\101", IF_X64},
    {I_BTC, 2, {RM_GPR|BITS16,IMMEDIATE,0,0}, "\320\2\x0F\xBA\207\25", IF_386|IF_SB},
    {I_BTC, 2, {RM_GPR|BITS32,IMMEDIATE,0,0}, "\321\2\x0F\xBA\207\25", IF_386|IF_SB},
    {I_BTC, 2, {RM_GPR|BITS64,IMMEDIATE,0,0}, "\324\2\x0F\xBA\207\25", IF_X64|IF_SB},
    ITEMPLATE_END
};

static const struct itemplate instrux_BTR[] = {
    {I_BTR, 2, {MEMORY,REG16,0,0}, "\320\2\x0F\xB3\101", IF_386|IF_SM},
    {I_BTR, 2, {REG16,REG16,0,0}, "\320\2\x0F\xB3\101", IF_386},
    {I_BTR, 2, {MEMORY,REG32,0,0}, "\321\2\x0F\xB3\101", IF_386|IF_SM},
    {I_BTR, 2, {REG32,REG32,0,0}, "\321\2\x0F\xB3\101", IF_386},
    {I_BTR, 2, {MEMORY,REG64,0,0}, "\324\2\x0F\xB3\101", IF_X64|IF_SM},
    {I_BTR, 2, {REG64,REG64,0,0}, "\324\2\x0F\xB3\101", IF_X64},
    {I_BTR, 2, {RM_GPR|BITS16,IMMEDIATE,0,0}, "\320\2\x0F\xBA\206\25", IF_386|IF_SB},
    {I_BTR, 2, {RM_GPR|BITS32,IMMEDIATE,0,0}, "\321\2\x0F\xBA\206\25", IF_386|IF_SB},
    {I_BTR, 2, {RM_GPR|BITS64,IMMEDIATE,0,0}, "\324\2\x0F\xBA\206\25", IF_X64|IF_SB},
    ITEMPLATE_END
};

static const struct itemplate instrux_BTS[] = {
    {I_BTS, 2, {MEMORY,REG16,0,0}, "\320\2\x0F\xAB\101", IF_386|IF_SM},
    {I_BTS, 2, {REG16,REG16,0,0}, "\320\2\x0F\xAB\101", IF_386},
    {I_BTS, 2, {MEMORY,REG32,0,0}, "\321\2\x0F\xAB\101", IF_386|IF_SM},
    {I_BTS, 2, {REG32,REG32,0,0}, "\321\2\x0F\xAB\101", IF_386},
    {I_BTS, 2, {MEMORY,REG64,0,0}, "\324\2\x0F\xAB\101", IF_X64|IF_SM},
    {I_BTS, 2, {REG64,REG64,0,0}, "\324\2\x0F\xAB\101", IF_X64},
    {I_BTS, 2, {RM_GPR|BITS16,IMMEDIATE,0,0}, "\320\2\x0F\xBA\205\25", IF_386|IF_SB},
    {I_BTS, 2, {RM_GPR|BITS32,IMMEDIATE,0,0}, "\321\2\x0F\xBA\205\25", IF_386|IF_SB},
    {I_BTS, 2, {RM_GPR|BITS64,IMMEDIATE,0,0}, "\324\2\x0F\xBA\205\25", IF_X64|IF_SB},
    ITEMPLATE_END
};

static const struct itemplate instrux_CALL[] = {
    {I_CALL, 1, {IMMEDIATE,0,0,0}, "\322\1\xE8\64", IF_8086},
    {I_CALL, 1, {IMMEDIATE|NEAR,0,0,0}, "\322\1\xE8\64", IF_8086},
    {I_CALL, 1, {IMMEDIATE|FAR,0,0,0}, "\322\1\x9A\34\74", IF_8086|IF_NOLONG},
    {I_CALL, 1, {IMMEDIATE|BITS16,0,0,0}, "\320\1\xE8\64", IF_8086},
    {I_CALL, 1, {IMMEDIATE|BITS16|NEAR,0,0,0}, "\320\1\xE8\64", IF_8086},
    {I_CALL, 1, {IMMEDIATE|BITS16|FAR,0,0,0}, "\320\1\x9A\34\74", IF_8086|IF_NOLONG},
    {I_CALL, 1, {IMMEDIATE|BITS32,0,0,0}, "\321\1\xE8\64", IF_386},
    {I_CALL, 1, {IMMEDIATE|BITS32|NEAR,0,0,0}, "\321\1\xE8\64", IF_386},
    {I_CALL, 1, {IMMEDIATE|BITS32|FAR,0,0,0}, "\321\1\x9A\34\74", IF_386|IF_NOLONG},
    {I_CALL, 2, {IMMEDIATE|COLON,IMMEDIATE,0,0}, "\322\1\x9A\35\30", IF_8086|IF_NOLONG},
    {I_CALL, 2, {IMMEDIATE|BITS16|COLON,IMMEDIATE,0,0}, "\320\1\x9A\31\30", IF_8086|IF_NOLONG},
    {I_CALL, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS16,0,0}, "\320\1\x9A\31\30", IF_8086|IF_NOLONG},
    {I_CALL, 2, {IMMEDIATE|BITS32|COLON,IMMEDIATE,0,0}, "\321\1\x9A\41\30", IF_386|IF_NOLONG},
    {I_CALL, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS32,0,0}, "\321\1\x9A\41\30", IF_386|IF_NOLONG},
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